Intel 386 - Manual (Page 689)

INTEL386™ EX MICROPROCESSOR USER’S MANUAL
Index-10
mode 3, 10-12 – 10-15
basic operation, 10-13 – 10-14
basic operation (odd count), 10-14
disabling the count, 10-14
writing a new count, 10-15
mode 4, 10-16 – 10-17
basic operation, 10-16
disabling the count, 10-17
writing a new count, 10-17
mode 5, 10-18 – 10-19
basic operation, 10-18
retriggering the strobe, 10-19
writing a new count, 10-19
operation, 10-5 – 10-19
operations caused by GATEn, 10-6
overview, 10-1 – 10-4
programming
considerations, 10-33
initializing the counters, 10-24–10-25 ,
D-63
input and output signals, 10-20 – 10-23
reading the counter, 10-27 – 10-33
counter-latch command, 10-27
read-back command, 10-30
simple read, 10-27
TMRCFG, 5-13 , 10-21 , D-62
TMRCON, 10-25 , 10-28 , D-63
TMRn, 10-29, 10-32, D-64, D-65
writing the counters,
10-26
rate generator, See Mode 2
read-back commands, multiple, 10-33
register addresses, 4-16 , D-2
registers, 10-4
TMRCON, 10-30
TMRn, 10-26
signals, 10-3
software-triggered strobe, See Mode 4
square wave, See Mode 3
Timing, 8-9
Timing diagram
basic external bus cycles, 6-6
basic internal and external bus cycles, 6-12
basic refresh cycle, 6-29
BS8 cycle, 6-33
counter mode 0, 10-7
counter mode 1, 10-9 , 10-10
counter mode 2, 10-11 , 10-12
counter mode 3, 10-13 , 10-14 , 10-15
counter mode 4, 10-16 , 10-17
counter mode 5, 10-18 , 10-19
DMA transfer, 12-9 , 12-11 , 12-21
entering and leaving idle mode, 8-9
entering and leaving powerdown mode, 8-11
HALT cycle, 6-27
interrupt acknowledge cycle, 6-25 , 9-29
JTAG test-logic unit, 18-12 , 18-13
LOCK# signal during pipelining, 6-35
nonpipelined read cycle, 6-15
nonpipelined write cycle, 6-18
pipelined cycles, 6-21
refresh cycle during HOLD/HLDA, 6-30
SSIO receiver, 13-15
SSIO transmitter, 13-11
U
Units of measure, defined, 1-3
V
Virtual-86 mode, 9-8
W
Watchdog timer unit, 17-1 – 17-16
block diagram, 17-2
design considerations, 17-12
disabling the WDT, 17-6
lockout sequence, 17-4
operation, 17-3 – 17-4
during idle mode, 8-5
overview, 17-1 – 17-2
programming, 17-5 – 17-6
bus monitor mode, 17-5
general-purpose timer mode, 17-4
software watchdog mode, 17-5
WDTCNTH, 17-8 , D-67
WDTCNTL, 17-8 , D-67
WDTRLDH, 17-10 , D-68
WDTRLDL, 17-10 , D-68
WDTSTATUS, 17-9 , D-69
register addresses, 4-18 , D-4