Intel 386 - Manual (Page 201)

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
9-2
The slave 82C59A is cascaded from (or connected to) the master’s IR2 signal. Like the master,
the slave uses a programmable priority structure. When the slave receives an interrupt request, it
sends the request to the master (assuming the request is enabled and has sufficient priority). The
master sees the slave request as a request on its IR2 line. The master then sends the request to the
core (assuming the request is enabled and has sufficient priority) and the core initiates an internal
interrupt acknowledge cycle.
The internal interrupt acknowledge cycle consists of two pulses that are sent to the 82C59A IN-
TA# inputs. This cycle causes the 82C59A that received the original interrupt request to put the
request’s vector number on the bus. The master’s cascade signals (CAS2:0) determine which
82C59A is being acknowledged (i.e., which 82C59A needs to put the vector number on the bus).
The core uses its processing mode (real or protected) and the vector number to find the address
of the interrupt service routine.
The master 82C59A has six device pins (INT9:8, INT3:0) connected to it. You can cascade addi-
tional external 82C59A slaves to these pins to increase the number of possible interrupt sources.
The external interrupt signals, INT9:8, are multiplexed with the internal asynchronous serial I/O
interrupt signals, SIOINT0 and SIOINT1. On the slave 82C59A, the external interrupt signal,
INT6, and the DMA Unit’s DMAINT signal, can be swapped before connecting to the slave’s IR4
and IR5 inputs (see Figure 9-1). The core initiates interrupt acknowledge cycles for the internal
82C59As. External logic must decode the bus signals (M/IO#, D/C#, W/R# and REFRESH#, see
Table 6-2 on page 6-5) to generate external interrupt acknowledge signals. Since the cascade bus
determines which 82C59A is being acknowledged, each external slave must monitor the master’s
cascade signals to determine whether it is the acknowledged slave. For external slaves, the mas-
ter’s cascade signals (CAS2:0) can be driven (using bit 7 of the INTCFG register) onto the
A18:16 address pins.
NOTE
Since external 82C59As require the CAS2:0 signals to stay valid through the
idle states that occur between the two interrupt acknowledge cycles, and since
the processor drives these lines high during these idle states, the CAS2:0 lines
must be latched externally to ensure validity during the idle states.