Intel 386 - Manual (Page 483)

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
16-4
The output of the Pin Configuration latch (PnCFG) selects whether the I/O port or peripheral is
connected to the pin. When the port is programmed to act as a peripheral pin, both the data for
the pin and the directional control signal for the pin come from the associated integrated periph-
eral. When a bi-directional port pin is programmed as an I/O port, all port parameters are under
software control.
The output of the Port Direction latch (PnDIR) enables or disables the three-state output driver
when the pin is programmed as an I/O port. The three-state output driver is enabled by clearing
the Port Direction latch. The data driven to an output port pin is held in the Port Data latch. Setting
the Port Direction latch disables the three-state output driver making the pin an input.
The signal present on the pin is routed through a synchronizer to a three-state buffer that connects
the I/O port path to the internal data bus. Not all peripheral input functions are synchronous. For
example, the interrupt pins (INT9-INT0) are asynchronous so that they can wake up the chip from
Powerdown mode when the clocks are stopped.
The state of the pin can be read at any time regardless of whether the pin is used as an I/O port or
for a peripheral function.