Intel 386 - Manual (Page 627)

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL
D-62
D.63 SSIOTBUF
D.64 TBR n
Transmit Holding Buffer
SSIOTBUF
(read/write) Expanded Addr:
ISA Addr:
Reset State: F480H
—
0000H
15 8
TB15 TB14 TB13 TB12 TB11 TB10 TB9 TB8
7 0
TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0
Bit
Number
Bit
Mnemonic
Function
15–0 TB15:0 Transmit Buffer Bits:
These bits make up the next data word to be transmitted. The control
logic loads this word into the transmit shift register. The transmit shift
register shifts the bits out on the falling edge of the tranmitter clock pin.
The word is transmitted out starting with the most-significant bit (TB15).
Transmit Buffer
TBR0, TBR1
(write only)
Expanded Addr:
ISA Addr:
Reset State:
TBR0 TBR1
F4F8H F8F8H
03F8H 02F8H
XXH XXH
7 0
TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0
Bit
Number
Bit
Mnemonic
Function
7–0 TB7:0 Transmit Buffer Bits:
These bits make up the next data word to be transmitted. The transmitter
loads this word into the transmit shift register. The transmit shift register
then shifts the bits out, along with the asynchronous communication bits
(start, stop, and parity). The data bits are shifted out least-significant bit
(TB0) first.
NOTE: The transmit buffer register shares an address port with other SIO registers. You must clear
bit 7 (DLAB) of LCR
n before you can write to the transmit buffer register.