Texas Instruments TMS320TCI648x - Manual (Page 106)

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SRIO Registers
Table 40. Serial RapidIO (SRIO) Registers (continued)
Offset Acronym Register Description Section
063Ch QUEUE15_RXDMA_HDP Queue Receive DMA Head Descriptor Pointer Register 15 Section 5.43
0680h QUEUE0_RXDMA_CP Queue Receive DMA Completion Pointer Register 0 Section 5.44
0684h QUEUE1_RXDMA_CP Queue Receive DMA Completion Pointer Register 1 Section 5.44
0688h QUEUE2_RXDMA_CP Queue Receive DMA Completion Pointer Register 2 Section 5.44
068Ch QUEUE3_RXDMA_CP Queue Receive DMA Completion Pointer Register 3 Section 5.44
0690h QUEUE4_RXDMA_CP Queue Receive DMA Completion Pointer Register 4 Section 5.44
0694h QUEUE5_RXDMA_CP Queue Receive DMA Completion Pointer Register 5 Section 5.44
0698h QUEUE6_RXDMA_CP Queue Receive DMA Completion Pointer Register 6 Section 5.44
069Ch QUEUE7_RXDMA_CP Queue Receive DMA Completion Pointer Register 7 Section 5.44
06A0h QUEUE8_RXDMA_CP Queue Receive DMA Completion Pointer Register 8 Section 5.44
06A4h QUEUE9_RXDMA_CP Queue Receive DMA Completion Pointer Register 9 Section 5.44
06A8h QUEUE10_RXDMA_CP Queue Receive DMA Completion Pointer Register 10 Section 5.44
06ACh QUEUE11_RXDMA_CP Queue Receive DMA Completion Pointer Register 11 Section 5.44
06B0h QUEUE12_RXDMA_CP Queue Receive DMA Completion Pointer Register 12 Section 5.44
06B4h QUEUE13_RXDMA_CP Queue Receive DMA Completion Pointer Register 13 Section 5.44
06B8h QUEUE14_RXDMA_CP Queue Receive DMA Completion Pointer Register 14 Section 5.44
06BCh QUEUE15_RXDMA_CP Queue Receive DMA Completion Pointer Register 15 Section 5.44
0700h TX_QUEUE_TEAR_DOWN Transmit Queue Teardown Register Section 5.45
0704h TX_CPPI_FLOW_MASKS0 Transmit CPPI Supported Flow Mask Register 0 Section 5.46
0708h TX_CPPI_FLOW_MASKS1 Transmit CPPI Supported Flow Mask Register 1 Section 5.46
070Ch TX_CPPI_FLOW_MASKS2 Transmit CPPI Supported Flow Mask Register 2 Section 5.46
0710h TX_CPPI_FLOW_MASKS3 Transmit CPPI Supported Flow Mask Register 3 Section 5.46
0714h TX_CPPI_FLOW_MASKS4 Transmit CPPI Supported Flow Mask Register 4 Section 5.46
0718h TX_CPPI_FLOW_MASKS5 Transmit CPPI Supported Flow Mask Register 5 Section 5.46
071Ch TX_CPPI_FLOW_MASKS6 Transmit CPPI Supported Flow Mask Register 6 Section 5.46
0720h TX_CPPI_FLOW_MASKS7 Transmit CPPI Supported Flow Mask Register 7 Section 5.46
0740h RX_QUEUE_TEAR_DOWN Receive Queue Teardown Register Section 5.47
0744h RX_CPPI_CNTL Receive CPPI Control Register Section 5.48
07E0h TX_QUEUE_CNTL0 Transmit CPPI Weighted Round Robin Control Register 0 Section 5.49
07E4h TX_QUEUE_CNTL1 Transmit CPPI Weighted Round Robin Control Register 1 Section 5.49
07E8h TX_QUEUE_CNTL2 Transmit CPPI Weighted Round Robin Control Register 2 Section 5.49
07ECh TX_QUEUE_CNTL3 Transmit CPPI Weighted Round Robin Control Register 3 Section 5.49
0800h RXU_MAP_L0 MailBox-to-Queue Mapping Register L0 Section 5.50
0804h RXU_MAP_H0 MailBox-to-Queue Mapping Register H0 Section 5.50
0808h RXU_MAP_L1 MailBox-to-Queue Mapping Register L1 Section 5.50
080Ch RXU_MAP_H1 MailBox-to-Queue Mapping Register H1 Section 5.50
0810h RXU_MAP_L2 MailBox-to-Queue Mapping Register L2 Section 5.50
0814h RXU_MAP_H2 MailBox-to-Queue Mapping Register H2 Section 5.50
0818h RXU_MAP_L3 MailBox-to-Queue Mapping Register L3 Section 5.50
081Ch RXU_MAP_H3 MailBox-to-Queue Mapping Register H3 Section 5.50
0820h RXU_MAP_L4 MailBox-to-Queue Mapping Register L4 Section 5.50
0824h RXU_MAP_H4 MailBox-to-Queue Mapping Register H4 Section 5.50
0828h RXU_MAP_L5 MailBox-to-Queue Mapping Register L5 Section 5.50
082Ch RXU_MAP_H5 MailBox-to-Queue Mapping Register H5 Section 5.50
0830h RXU_MAP_L6 MailBox-to-Queue Mapping Register L6 Section 5.50
0834h RXU_MAP_H6 MailBox-to-Queue Mapping Register H6 Section 5.50
106 Serial RapidIO (SRIO) SPRUE13A – September 2006
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