Texas Instruments TMS320TCI648x - Manual (Page 215)

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5.78 Logical/Transport Layer Address Capture CSR (ADDR_CAPT)
SRIO Registers
The logical/transport layer address capture CSR (ADDR_CAPT) is shown in Figure 141 and described in
Table 154 .
Figure 141. Logical/Transport Layer Address Capture CSR (ADDR_CAPT) - Address Offset 2014h
31 16
ADDRESS_31_3
R-0000h
15 3 2 1 0
ADDRESS_31_3 Reserved XAMSBS
R-0000h R-0 R-00
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 154. Logical/Transport Layer Address Capture CSR (ADDR_CAPT) Field Descriptions
Bit Field Value Description
31–3 ADDRESS_31_3 00000000h Least significant 29 bits of the address associated with the error
to
1FFFFFFFh
2 Reserved 0 This read-only bit returns 0 when read.
1–0 XAMSBS 00b–11b Extended address bits of the address associated with the error
SPRUE13A – September 2006 Serial RapidIO (SRIO) 215
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