Texas Instruments TMS320TCI648x - Manual (Page 72)

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SRIO Functional Description
Table 27. Global Enable and Global Enable Status Field Descriptions
Register (Bit) Field Value Description
GBL_EN(31–1) Reserved 0 These read-only bits return 0s when read.
GBL_EN(0) EN Global enable. This bit controls reset to all clock domains within the
peripheral.
0 The peripheral is to be disabled (held in reset with clocks disabled).
1 The peripheral is to be enabled.
GBL_EN_STAT(31–10) Reserved 0 These read-only bits return 0s when read.
GBL_EN_STAT(9) BLK8_EN_STAT Block 8 enable status. Logical block 8 is SRIO port 3.
0 Logical block 8 is in reset with its clock off.
1 Logical block 8 is enabled with its clock running.
GBL_EN_STAT(8) BLK7_EN_STAT Block 7 enable status. Logical block 7 is SRIO port 2.
0 Logical block 7 is in reset with its clock off.
1 Logical block 7 is enabled with its clock running.
GBL_EN_STAT(7) BLK6_EN_STAT Block 6 enable status. Logical block 6 is SRIO port 1.
0 Logical block 6 is in reset with its clock off.
1 Logical block 6 is enabled with its clock running.
GBL_EN_STAT(6) BLK5_EN_STAT Block 5 enable status. Logical block 5 is SRIO port 0.
0 Logical block 5 is in reset with its clock off.
1 Logical block 5 is enabled with its clock running.
GBL_EN_STAT(5) BLK4_EN_STAT Block 4 enable status. Logical block 4 is the message receive unit (RXU).
0 Logical block 4 is in reset with its clock off.
1 Logical block 4 is enabled with its clock running.
GBL_EN_STAT(4) BLK3_EN_STAT Block 3 enable status. Logical block 3 is the message transmit unit (TXU).
0 Logical block 3 is in reset with its clock off.
1 Logical block 3 is enabled with clock running.
GBL_EN_STAT(3) BLK2_EN_STAT Block 2 enable status. Logical block 2 is the memory access unit (MAU).
0 Logical block 2 is in reset with its clock off.
1 Logical block 2 is enabled with its clock running.
GBL_EN_STAT(2) BLK1_EN_STAT Block 1 enable status. Logical block 1 is the Load/Store module, which is
comprised of the four Load/Store units (LSU1, LSU2, LSU3, and LSU4).
0 Logical block 1 is in reset with its clock off.
1 Logical block 1 is enabled with its clock running.
GBL_EN_STAT(1) BLK0_EN_STAT Block 0 enable status. Logical block 0 is the set of memory-mapped control
registers for the SRIO peripheral.
0 Logical block 0 is in reset with its clock off.
1 Logical block 0 is enabled with its clock running.
GBL_EN_STAT(0) GBL_EN_STAT Global enable status
0 The peripheral is in reset with all its clocks off.
1 The peripheral is enabled with all its clocks running.
The 18 block-specific registers are represented by Figure 34 through Figure 39 . These register pairs have
bits with the same functions, which are described in Table 28 .
Figure 34. BLK0_EN (Address 0038h)
31 1 0
Reserved EN
R-0 R/W-1
LEGEND: R = Read, W = Write, -n = Value after reset
Serial RapidIO (SRIO) 72 SPRUE13A – September 2006
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