Texas Instruments TMS320TCI648x - Manual (Page 198)

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5.67 Port Response Time-Out Control CSR (SP_RT_CTL)
SRIO Registers
The port response time-out control CSR (SP_RT_CTL) is shown in Figure 130 and described in Table 138
For additional programming information, see Section 2.3.3.3 and Section 2.3.3 .
Figure 130. Port Response Time-Out Control CSR (SP_RT_CTL) - Address Offset 1124h
31
TIMEOUT_VALUE
RW-FFFFFFh
8 7 0
TIMEOUT_VALUE Reserved
RW-FFFFFFh R-00h
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 138. Port Response Time-Out Control CSR (SP_RT_CTL) Field Descriptions
Bit Field Value Description
31–8 TIMEOUT_VALUE 000000h Timeout value for all ports on the device. This timeout is for sending a packet to
to receiving the corresponding response packet. Max value represents 3 to 6
FFFFFFh seconds. The timeout duration can be expressed as:
Timeout = 15 x ((Prescale Value + 1) x DMA Clock Period x Timeout Value)
where Prescale value is set in PER_SET_CNTL (offset 0020h) and the Timeout
value is the decimal representation of this register value. For example, given a
400-MHz DMA, a Prescale Value of 4, and a Timeout Value of FFFFFFh, the
Timeout duration would be:
Timeout = 15 x ((4 + 1) x 2.5 ns x 16777216) = 3.15 s
7–0 Reserved 00h These read-only bits return 0s when read.
Serial RapidIO (SRIO) 198 SPRUE13A – September 2006
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