Texas Instruments TMS320TCI648x - Manual (Page 96)

www.ti.com
4.4.1.3 Error, Reset, and Special Event Interrupt Condition Routing Registers
Interrupt Conditions
Figure 57. LSU Interrupt Condition Routing Registers
LSU Interrupt Condition Routing Register 0 (LSU_ICRR0) (Address Offset 02E0h)
31 28 27 24 23 20 19 16
ICR7 ICR6 ICR5 ICR4
R/W-0000 R/W-0000 R/W-0000 R/W-0000
15 12 11 8 7 4 3 0
ICR3 ICR2 ICR1 ICR0
R/W-0000 R/W-0000 R/W-0000 R/W-0000
LSU Interrupt Condition Routing Register 1 (LSU_ICRR1) (Address Offset 02E4h)
31 28 27 24 23 20 19 16
ICR15 ICR14 ICR13 ICR12
R/W-0000 R/W-0000 R/W-0000 R/W-0000
15 12 11 8 7 4 3 0
ICR11 ICR10 ICR9 ICR8
R/W-0000 R/W-0000 R/W-0000 R/W-0000
LSU Interrupt Condition Routing Register 2 (LSU_ICRR2) (Address Offset 02E8h)
31 28 27 24 23 20 19 16
ICR23 ICR22 ICR21 ICR20
R/W-0000 R/W-0000 R/W-0000 R/W-0000
15 12 11 8 7 4 3 0
ICR19 ICR18 ICR17 ICR16
R/W-0000 R/W-0000 R/W-0000 R/W-0000
LSU Interrupt Condition Routing Register 3 (LSU_ICRR3) (Address Offset 02ECh)
31 28 27 24 23 20 19 16
ICR31 ICR30 ICR29 ICR28
R/W-0000 R/W-0000 R/W-0000 R/W-0000
15 12 11 8 7 4 3 0
ICR27 ICR26 ICR25 ICR24
R/W-0000 R/W-0000 R/W-0000 R/W-0000
LEGEND: R/W = Read/Write; -n = Value after reset
The ICRRs shown in Figure 58 route port interrupt requests to interrupt destinations. For example, if
ICS8 = 1 in ERR_RST_EVNT_ICSR and ICR8 = 0001b in ERR_RST_EVNT_ICRR2, port 0 has generated
an error interrupt request, and that request is routed to interrupt destination 1.
96 Serial RapidIO (SRIO) SPRUE13A – September 2006
Submit Documentation Feedback