Texas Instruments TMS320TCI648x - Manual (Page 211)

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SRIO Registers
Table 151. Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions (continued)
Bit Field Value Description
25 MSG_REQ_TIMEOUT Message request timeout (endpoint device only)
0 A timeout has not been detected by RXU.
1 A timeout has been detected by the RXU. A required message request has not
been received by the RXU within the specified time-out interval. To clear this
bit, write 0 to it.
24 PKT_RSPNS_TIMEOUT Packet response timeout (endpoint device only)
0 A timeout has not been detected by an LSU or the TXU.
1 A timeout has been detected by an LSU or the TXU. A required response has
not been received by the LSU/TXU within the specified timeout interval. To
clear this bit, write 0 to it.
23 UNSOLICITED_RSPNS Unsolicited response (switch or endpoint device)
0 An unsolicited response packet has not been received by an LSU or the TXU.
1 An unsolicited response packet has been received by an LSU or the TXU. To
clear this bit, write 0 to it.
22 UNSUPPORTED_TRANS Unsupported transaction (switch or endpoint device)
0 The MAU has not received an unsupported transaction.
1 The MAU has received an unsupported transaction. That is, the MAU received
a transaction that is not supported in the destination operations CAR. To clear
this bit, write 0 to it.
21–8 Reserved 0 These read-only bits return 0 when read.
7 RX_CPPI_SECURITY RX CPPI security error
0 The RXU has not detected an access block.
1 The RXU has detected an access block. That is, access to one of the RX
queues was blocked. To clear this bit, write 0 to it.
6 RX_IO_DMA_ACCESS RX I/O DMA access error
0 A DMA access to the MAU has not been blocked.
1 A DMA access to the MAU was blocked. To clear this bit, write 0 to it.
5–0 Reserved 0 These read-only bits return 0 when read.
SPRUE13A – September 2006 Serial RapidIO (SRIO) 211
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