Table 20, Figure 22, Table 21 – Texas Instruments TMS320TCI648x User Manual

Page 52

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31

0

1

2

15

23

7

27

11

19

3

29

o

w

n
e

r

s
h

i

p

t

e
a

r

d
o

w

n

e
o
p

e
o
q

s
o
p

3

reserved

retry_count

cc

message_length

13

21

5

25

9

17

1

30

14

22

6

26

10

18

2

28

12

20

4

24

8

16

0

Bit Fields

next_descriptor_pointer

buffer_pointer

dest_id

pri

tt

ssize

mailbox

port_id

Word

Offset

SRIO Functional Description

Table 20. TX DMA State Completion Pointer (CP) (Address Offset 58h–5BCh)

Bit

Name

Description

31–0

TX Queue

TX Queue Completion Pointer: This field is the DSP core memory address for the transmit queue

Completion Pointer

completion pointer. This register is written by the DSP core with the buffer descriptor address for
the last buffer processed by the DSP core during interrupt processing. The port uses the value
written to determine if the interrupt should be deasserted.

Figure 22. TX Buffer Descriptor Fields

Table 21. TX Buffer Descriptor Field Definitions

Field

Description

next_descriptor_pointer

Next Descriptor Pointer: The 32-bit word aligned memory address of the next buffer
descriptor in the TX queue. This is the mechanism used to reference the next buffer
descriptor from the current buffer descriptor. If the value of this pointer is zero then the
current buffer is the last buffer in the queue. The DSP core sets the
next_descriptor_pointer.

buffer_pointer

Buffer Pointer: The byte aligned memory address of the buffer associated with the
buffer descriptor. The DSP core sets the buffer_pointer.

sop = 1

Start of Message: Indicates that the descriptor buffer is the first buffer in the message.

This bit will always be set as this device only supports one buffer per message.

eop = 1

End of Message: Indicates that the descriptor buffer is the last buffer in the message.

This bit will always be set as this device only supports one buffer per message.

ownership

Ownership: Indicates ownership of the message and is valid only on sop. This bit is set
by the DSP core and cleared by the port when the message has been transmitted. The
DSP core uses this bit to reclaim buffers.

0: The message is owned by the DSP core

1: The message is owned by the port

eoq

End Of Queue: Set by the port to indicate that all messages in the queue have been
transmitted and the TX queue is empty. End of queue is determined by the port when
the next_descriptor_pointer is zero on an eop buffer. This bit is valid only on eop.

0: The TX queue has more messages to transfer.

1: The Descriptor buffer is the last buffer in the last message in the queue.

teardown_complete

Teardown Complete: Set by the port to indicate that the DSP core commanded
teardown process is complete, and the channel buffers may be reclaimed by the DSP
core.

0: The port has not completed the teardown process.

1: The port has completed the commanded teardown process.

52

Serial RapidIO (SRIO)

SPRUE13A – September 2006

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