Texas Instruments TMS320TCI648x - Manual (Page 245)

SRIO Registers
ENPLL2 field of PER_SET_CNTL 113 register 142
ENPLL3 field of PER_SET_CNTL 113 ERROR response
ENPLL4 field of PER_SET_CNTL 113 during direct I/O reception 42
during message passing 43 ENPLL field of SERDES_CFGn_CNTL 130
error status interrupt to the CPU 85 ENRX field of SERDES_CFGRXn_CNTL 125
error type field for port n error capture 223 ENTX field of SERDES_CFGTXn_CNTL 128
EXTENDED_ADDRESSING_CONTROL field of eop field of RX buffer descriptor 47
PE_LL_CTL 190
eop field of TX buffer descriptor 52
EXTENDED_ADDRESSING_SUPPORT field of eoq field of RX buffer descriptor 47
PE_FEAT 186
eoq field of TX buffer descriptor 52
EXTENDED_FEATURES field of PE_FEAT 186
EQ field of SERDES_CFGRXn_CNTL 125
extended address 2 MSBs field for LSUn 159
equalizer control field 125
extended address LSB field for LSUn 156
ERR_DET 210
extended address MSB field for LSUn 155
ERR_EN 212
extended features ID field 196
ERR_MSG_FORMAT_ENABLE field of ERR_EN 212
EXTENDEDFEATURESPTR field of ASBLY_INFO 185
ERR_MSG_FORMAT field of ERR_DET 210
extended feature support field 186
ERR_RPT_BH 209
external device requirements 20
ERR_RST_EVNT_ICCR 143
ERR_RST_EVNT_ICRR 149
F
ERR_RST_EVNT_ICRR2 149
features not supported in SRIO peripheral 20
ERR_RST_EVNT_ICRR3 149
features supported in SRIO peripheral 19
ERR_RST_EVNT_ICSR 142
FIFOs
ERROR_CHECK_DISABLE field of SPn_CTL 206
in data path description for LSUs 39
ERROR_RATE_BIAS field of SPn_ERR_RATE 228
in direct I/O RX operation 42
ERROR_RATE_COUNTER field of SPn_ERR_RATE
in direct I/O TX operation 40
228
in Load/Store module data flow diagram 39 ERROR_RATE_DEGRADED_THRESH field of
SPn_ERR_THRESH 229 in message passing 43
ERROR_RATE_FAILED_THRESH field of in SRIO peripheral block diagram 21
SPn_ERR_THRESH 229 TX FIFO bypass field for ports 231
ERROR_RATE_RECOVERY field of SPn_ERR_RATE finding interrupt source with help from interrupt status
228 decode registers 97
ERROR_TYPE field of SPn_ERR_ATTR_CAPT_DBG0 fixed transmit clock phase enable bit 128
223
FLOW_CNTL_ID field of FLOW_CNTLn 181
error checking for ports
FLOW_CNTLn 181
general error checking disable field 207
FLOW_CONTROL_SUPPORT field of PE_FEAT 186
idle error checking disable field 231
FLOW_MASK field of LSUn_FLOW_MASKS 162
error handling and logging for logical/transport errors 83
flow control 65
error rate counter for port n
flow control enable bit
count value 228
for data flow in logical layer of peripheral 112
decrement rate 228
for port n transmit flow control 236
peak count value 228
flow control table entry register 181
threshold 228
flow masks
error rate counting enable register for port n 221
for CPPI (message) transmission 169
error rate thresholds for port n
for LSU transmission 162
broken link case 229
introduction 67
degraded link case 229
force insertion of control symbol in outbound packet 240
error recovery software option for port n 236
force reinitialization process for port n 236
error reporting block header register 209
format type associated with logical/transport error 217
error reporting thresholds for port n
FREE field of PCR 112
broken link case 229
free run bit 112
degraded link case 229
free run emulation mode 75
error, reset, and special event interrupt condition clear
frequency points of 1x/4x LP-Serial specification 18
register 143
frequency prescaler select field 114
error, reset, and special event interrupt condition routing
frequency range versus MPY value 30
registers 149
FTYPE field of CTRL_CAPT 217
error, reset, and special event interrupt condition status
Ftypes of SRIO packets 25
SPRUE13A – September 2006 Index 245
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