Texas Instruments TMS320TCI648x - Manual (Page 129)

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SRIO Registers
Table 60. SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL) Field
Descriptions (continued)
Bit Field Value Description
0 ENTX Enable transmitter
0 Disable this transmitter.
1 Enable this transmitter.
Table 61. DE Bits of SERDES_CFGTXn_CNTL
Amplitude Reduction
DE Bits % dB
0000b 0 0
0001b 4.76 –0.42
0010b 9.52 –0.87
0011b 14.28 –1.34
0100b 19.04 –1.83
0101b 23.8 –2.36
0110b 28.56 –2.92
0111b 33.32 –3.52
1000b 38.08 –4.16
1001b 42.85 –4.86
1010b 47.61 –5.61
1011b 52.38 –6.44
1100b 57.14 –7.35
1101b 61.9 –8.38
1110b 66.66 –9.54
1111b 71.42 –10.87
Table 62. SWING Bits of SERDES_CFGTXn_CNTL
SWING Bits Amplitude (mV
dfpp
)
000b 125
001b 250
010b 500
011b 625
100b 750
101b 1000
110b 1125
111b 1250
SPRUE13A – September 2006 Serial RapidIO (SRIO) 129
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