4 srio packet type, 2 srio pins, Pins – Texas Instruments TMS320TCI648x User Manual

Page 25

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2.1.2.4

SRIO Packet Type

2.2

SRIO Pins

SRIO Functional Description

The type of received packet determines how the packet routing is handled. Reserved or undefined packet
types are destroyed before being processed by the logical layer functional blocks. This prevents erroneous
allocation of resources to them. Unsupported packet types are responded to with an error response
packet.

Section 2.1.2.4

details the handling of such packets.

The type of SRIO packet is determined by the combination of Ftype and Ttype fields in the packet.

Table 3

lists all supported combinations of Ftype/Ttype and the corresponding decoded actions on the packets.

Table 3. Packet Types

Ftype

Ttype

Packet Type

Ftype = 0

Ttype = don't care

Ftype = 2

Ttype = 0100b

NREAD

Ttype = 1100b

Atomic increment

Ttype = 1101b

Atomic decrement

Ttype = 1110b

Atomic set

Ttype = 1111b

Atomic clear

Ttype = others

Ftype = 5

Ttype = 0100b

NWRITE

Ttype = 0101b

NWRITE_R

Ttype = 1110b

Atomic test and swap

Ttype = others

Ftype = 6

Ttype = don't care

SWRITE

Ftype = 7

Ttype = don't care

Congestion control

Ftype = 8

Ttype = 0000b

Maintenance read

Ttype = 0001b

Maintenance write

Ttype = 0010b

Maintenance read response

Ttype = 0011b

Maintenance write response

Ttype = 0100b

Maintenance port-write

Ttype = others

Ftype = 10

Ttype = don't care

Doorbell

Ftype = 11

Ttype = don't care

Message

Ftype = 13

Ttype = 0000b

Response(+Doorbell Resp)

Ttype = 0001b

Message Response

Ttype = 1000b

Response w/payload

Ttype = other

Undefined Ftypes: 1,3,4,9,12,14,15

The SRIO device pins are high-speed differential signals based on Current-Mode Logic (CML) switching
levels. The transmit and receive buffers are self-contained within the clock recovery blocks. The reference
clock input is not incorporated into the SERDES macro. It uses a differential input buffer that is compatible
with the LVDS and LVPECL interfaces available from crystal oscillator manufacturers.

Table 4

describes

the device pins for the SRIO peripheral.

SPRUE13A – September 2006

Serial RapidIO (SRIO)

25

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