Texas Instruments TMS320TCI648x - Manual (Page 168)

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5.45 Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN)
SRIO Registers
Each bit in this register corresponds to one of the 16 TX buffer descriptor queues. If a 1 is written to a bit,
the teardown process is initiated for the associated queue. TX_QUEUE_TEAR_DOWN is shown in
Figure 107 and described in Table 112 .
Figure 107. Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) - Address Offset 0700h
31 16
Reserved
R-0000h
15 14 13 12 11 10 9 8
QUEUE15_ QUEUE14_ QUEUE13_ QUEUE12_ QUEUE11_ QUEUE10_ QUEUE9_ QUEUE8_
TEAR_DWN TEAR_DWN TEAR_DWN TEAR_DWN TEAR_DWN TEAR_DWN TEAR_DWN TEAR_DWN
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
7 6 5 4 3 2 1 0
QUEUE7_ QUEUE6_ QUEUE5_ QUEUE4_ QUEUE3_ QUEUE2_ QUEUE1_ QUEUE0_
TEAR_DWN TEAR_DWN TEAR_DWN TEAR_DWN TEAR_DWN TEAR_DWN TEAR_DWN TEAR_DWN
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
LEGEND: R = Read only; W = Write only; -n = Value after reset
Table 112. Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) Field Descriptions
Bit Field Value Description
31–16 Reserved 0 These read-oinly bits return 0s when read.
15–0 QUEUEn_TEAR_DWN Queue n tear down
(n = 15 to 0)
0 No effect
1 Tear down Queue n.
Serial RapidIO (SRIO) 168 SPRUE13A – September 2006
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