Texas Instruments TMS320TCI648x - Manual (Page 99)

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4.6 Interrupt Generation
4.7 Interrupt Pacing
Interrupt Conditions
Figure 61. Example Diagram of Interrupt Status Decode Register Mapping
The following are suggestions for minimizing the number of register reads to identifying the interrupt
source:
•
Dedicate each doorbell ICSR to one core. The CPU can then determine the interrupt source from a
single read of the decode register.
•
Assign the RX and TX CPPI queues orthogonally to different cores. The CPU can then determine the
interrupt source from a single read of the decode registers. The only exceptions to this are bits 31 and
30, which are also logically ORed with LSU and port interrupt sources.
Interrupts are triggered on a 0-to-1 logic-signal transition. Regardless of the interrupt sources, the physical
interrupts are set only when the total number of set ICSR bits transitions from none to one or more. The
peripheral is responsible for setting the correct bit within the ICSR. The ICRR register maps the pending
interrupt request to the appropriate physical interrupt line. The corresponding CPU is interrupted and
reads the ISDR and ICSR registers to determine the interrupt source and appropriate action. Interrupt
generation is governed by the interrupt pacing discussed
Section 4.7 .
The rate at which an interrupt can be generated is controllable for each physical interrupt destination. Rate
control is implemented with a programmable down-counter. The load value of the counter is written by the
CPU into the appropriate interrupt rate control register (see
Figure 62 ). The counter reloads and
SPRUE13A – September 2006 Serial RapidIO (SRIO) 99
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