Texas Instruments TMS320TCI648x - Manual (Page 138)

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5.22 LSU Interrupt Condition Status Register (LSU_ICSR)
SRIO Registers
Each of the status bits in this register indicates the occurrence of a particular type of transaction interrupt
condition for a particular LSU. LSU_ICSR is shown in
Figure 83 and described in Table 73 . For additional
programming information, see Section 4.3.3 .
Figure 83. LSU Interrupt Condition Status Register (LSU_ICSR) - Address Offset 0260h
<--------------------------------- Bits for LSU4 ---------------------------------> <--------------------------------- Bits for LSU3 --------------------------------->
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICS31 ICS30 ICS29 ICS28 ICS27 ICS26 ICS25 ICS24 ICS23 ICS22 ICS21 ICS20 ICS19 ICS18 ICS17 ICS16
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
<--------------------------------- Bits for LSU2 ---------------------------------> <--------------------------------- Bits for LSU1 --------------------------------->
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9 ICS8 ICS7 ICS6 ICS5 ICS4 ICS3 ICS2 ICS1 ICS0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = Value after reset
Table 73. LSU Interrupt Condition Status Register (LSU_ICSR) Field Descriptions
Bit Field Value Description
31 ICS31 0 LSU4 interrupt condition not detected.
1 LSU4 interrupt condition detected. Packet not sent due to unavailable outbound credit at given
priority.
30 ICS30 0 LSU4 interrupt condition not detected.
1 LSU4 interrupt condition detected. Retry Doorbell response received or Atomic test-and-swap was
not allowed (semaphore in use).
29 ICS29 0 LSU4 interrupt condition not detected.
1 LSU4 interrupt condition detected. Transaction was not sent due to DMA data transfer error.
28 ICS28 0 LSU4 interrupt condition not detected.
1 LSU4 interrupt condition detected. Transaction timeout occurred.
27 ICS27 0 LSU4 interrupt condition not detected.
1 LSU4 interrupt condition detected. Transaction was not sent due to unsupported transaction type or
invalid field encoding.
26 ICS26 0 LSU4 interrupt condition not detected.
1 LSU4 interrupt condition detected. Transaction was not sent due to Xoff condition.
25 ICS25 0 LSU4 interrupt condition not detected.
1 LSU4 interrupt condition detected. Non-posted transaction received ERROR response, or error in
response payload.
24 ICS24 0 LSU4 interrupt condition not detected.
1 LSU4 interrupt condition detected. Transaction complete, No errors (posted/non-posted). Enable for
this interrupt is ultimately controlled by the Interrupt Req bit of LSU4_REG4. This allows
enabling/disabling on a per request basis. For optimum LSU performance, interrupt pacing should
not be used on the LSU interrupts.
23 ICS23 0 LSU3 interrupt condition not detected.
1 LSU3 interrupt condition detected. Packet not sent due to unavailable outbound credit at given
priority.
22 ICS22 0 LSU3 interrupt condition not detected.
1 LSU3 interrupt condition detected. Retry Doorbell response received or Atomic test-and-swap was
not allowed (semaphore in use).
21 ICS21 0 LSU3 interrupt condition not detected.
1 LSU3 interrupt condition detected. Transaction was not sent due to DMA data transfer error.
20 ICS20 0 LSU3 interrupt condition not detected.
1 LSU3 interrupt condition detected. Transaction timeout occurred.
138 Serial RapidIO (SRIO) SPRUE13A – September 2006
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