Texas Instruments TMS320TCI648x - Manual (Page 133)

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5.17 DOORBELLn Interrupt Condition Clear Register (DOORBELLn_ICCR)
SRIO Registers
The four doorbells interrupts that are mapped are cleared by this register (see Table 67 ). The general form
of a doorbell interrupt condition clear register is shown in Figure 78 and described in Table 68 . For
additional programming information, see Section 4.4.1 and Section 2.3.6 .
Table 67. DOORBELLn_ICCR Registers
Register Address Offset
DOORBELL0_ICCR 0208h
DOORBELL1_ICCR 0218h
DOORBELL2_ICCR 0228h
DOORBELL3_ICCR 0238h
Figure 78. Doorbell n Interrupt Condition Clear Register (DOORBELLn_ICCR)
31 16
Reserved
R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICC15 ICC14 ICC13 ICC12 ICC11 ICC10 ICC9 ICC8 ICC7 ICC6 ICC5 ICC4 ICC3 ICC2 ICC1 ICC0
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
LEGEND: W = Write only; R = Read only; -n = Value after reset
Table 68. DOORBELLn Interrupt Condition Clear Register (DOORBELLn_ICCR) Field Descriptions
Bit Field Value Description
31–16 Reserved 0 These read-only bits return 0s when read.
15–0 ICCx Doorbell n interrupt condition clear bit
(x = 15 to 0)
0 No effect
1 Clear bit x of the corresponding doorbell interrupt condition status register
(ICSR).
SPRUE13A – September 2006 Serial RapidIO (SRIO) 133
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