Texas Instruments TMS320TCI648x - Manual (Page 12)

99 LSUn_REG6 Registers and the Associated LSUs
...................................................................
161
100 LSUn Control Register 6 (LSUn_REG6) Field Descriptions ........................................................ 161
101 LSUn_FLOW_MASKS Registers and the Associated LSUs ........................................................ 162
102 LSUn Congestion Control Flow Mask Register (LSUn_FLOW_MASKS) Field Descriptions
...................
162
103 LSUn FLOW_MASK Fields
..............................................................................................
162
104 QUEUEn_TXDMA_HDP Registers ..................................................................................... 164
105 Queue n Transmit DMA Head Descriptor Pointer Register (QUEUEn_TXDMA_HDP) Field Descriptions ... 164
106 QUEUEn_TXDMA_CP Registers
.......................................................................................
165
107 Queue Transmit DMA Completion Pointer Registers (QUEUEn_TXDMA_CP) Field Descriptions ............ 165
108 QUEUEn_RXDMA_HDP Registers ..................................................................................... 166
109 Queue n Receive DMA Head Descriptor Pointer Register (QUEUEn_RXDMA_HDP) Field Descriptions ... 166
110 QUEUEn_RXDMA_CP Registers
......................................................................................
167
111 Queue n Receive DMA Completion Pointer Register (QUEUEn_RXDMA_CP) Field Descriptions ........... 167
112 Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) Field Descriptions ......................... 168
113 TX_CPPI_FLOW_MASKS Registers and the Associated TX Queues ............................................ 169
114 TX Queue n FLOW_MASK Field Descriptions
........................................................................
170
115 Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) Field Descriptions ......................... 172
116 Receive CPPI Control Register (RX_CPPI_CNTL) Field Descriptions ............................................ 173
117 Transmit CPPI Weighted Round Robin Control Register Field Descriptions
.....................................
175
118 Mailbox to Queue Mapping Registers and the Associated RX Mappers
..........................................
177
119 Mailbox-to-Queue Mapping Register Ln (RXU_MAP_Ln) Field Descriptions ..................................... 179
120 Mailbox-to-Queue Mapping Register Hn (RXU_MAP_Hn) Field Descriptions .................................... 179
121 FLOW_CNTLn Registers
................................................................................................
181
122 Flow Control Table Entry Register n (FLOW_CNTLn) Field Descriptions
........................................
181
123 Device Identity CAR (DEV_ID) Field Descriptions ................................................................... 182
124 Device Information CAR (DEV_INFO) Field Descriptions ........................................................... 183
125 Assembly Identity CAR (ASBLY_ID) Field Descriptions
.............................................................
184
126 Assembly Information CAR (ASBLY_INFO) Field Descriptions .................................................... 185
127 Processing Element Features CAR (PE_FEAT) Field Descriptions ............................................... 186
128 Source Operations CAR (SRC_OP) Field Descriptions ............................................................. 188
129 Destination Operations CAR (DEST_OP) Field Descriptions
.......................................................
189
130 Processing Element Logical Layer Control CSR (PE_LL_CTL) Field Descriptions .............................. 190
131 Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) Field Descriptions ...................... 191
132 Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) Field Descriptions ........................ 192
133 Base Device ID CSR (BASE_ID) Field Descriptions
.................................................................
193
134 Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) Field Descriptions .................................. 194
135 Component Tag CSR (COMP_TAG) Field Descriptions ............................................................ 195
136 1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD) Field Descriptions
..............
196
137 Port Link Timeout Control CSR (SP_LT_CTL) Field Descriptions
.................................................
197
138 Port Response Time-Out Control CSR (SP_RT_CTL) Field Descriptions ........................................ 198
139 Port General Control CSR (SP_GEN_CTL) Field Descriptions .................................................... 199
140 SPn_LM_REQ Registers and the Associated Ports
.................................................................
200
141 Port Link Maintenance Request CSR n (SPn_LM_REQ) Field Descriptions
.....................................
200
142 SPn_LM_RESP Registers and the Associated Ports ................................................................ 201
143 Port Link Maintenance Response CSR n (SPn_LM_RESP) Field Descriptions ................................. 201
144 SPn_ACKID_STAT Registers and the Associated Ports
............................................................
202
145 Port Local AckID Status CSR n (SPn_ACKID_STAT) Field Descriptions ......................................... 202
146 SPn_ERR_STAT Registers and the Associated Ports .............................................................. 203
147 Port Error and Status CSR n (SPn_ERR_STAT) Field Descriptions .............................................. 203
148 SPn_CTL Registers and the Associated Ports
.......................................................................
206
149 Port Control CSR n (SPn_CTL) Field Descriptions .................................................................. 206
12 List of Tables SPRUE13A – September 2006
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