Texas Instruments TMS320TCI648x - Manual (Page 115)

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SRIO Registers
Table 43. Peripheral Settings Control Register (PER_SET_CNTL) Field Descriptions (continued)
Bit Field Value Description
3 ENPLL4 0 Not used. Should always be programmed as "0". See Section 2.3.2.1 to
enable SERDES PLL.
2 ENPLL3 0 Not used. Should always be programmed as "0". See Section 2.3.2.1 to
enable SERDES PLL.
1 ENPLL2 0 Not used. Should always be programmed as "0". See Section 2.3.2.1 to
enable SERDES PLL.
0 ENPLL1 0 Not used. Should always be programmed as "0". See Section 2.3.2.1 to
enable SERDES PLL.
SPRUE13A – September 2006 Serial RapidIO (SRIO) 115
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