Texas Instruments TMS320TCI648x - Manual (Page 201)

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5.70 Port Link Maintenance Response CSR n (SPn_LM_RESP)
SRIO Registers
Each of the four ports is supported by a register of this type (see Table 142 ). The port link maintenance
response CSR n (SPn_LM_RESP) is shown in Figure 133 and described in Table 143 .
Table 142. SPn_LM_RESP Registers and the Associated Ports
Register Address Offset Associated Port
SP0_LM_RESP 1144h Port 0
SP1_LM_RESP 1164h Port 1
SP2_LM_RESP 1184h Port 2
SP3_LM_RESP 11A4h Port 3
Figure 133. Port Link Maintenance Response CSR n (SPn_LM_RESP)
31 30 16
RESPONSE_
Reserved
VALID
R-0 R-0
15 10 9 5 4 0
Reserved ACKID_STATUS LINK_STATUS
R-0 R-0 R-0
LEGEND: R = Read only; -n = Value after reset
Table 143. Port Link Maintenance Response CSR n (SPn_LM_RESP) Field Descriptions
Bit Field Value Description
31 RESPONSE_VALID If the link-request causes a link-response, this bit indicates that the
link-response has been received and the status fields are valid. If the
link-request does not cause a link-response, this bit indicates that the
link-request has been transmitted. This bit automatically clears on read.
30–10 Reserved 0 These read-only bits return 0s when read.
9–5 ACKID_STATUS 00000b–11111b AckID status field from the link-response control symbol
4–0 LINK_STATUS 00000b–11111b Link status field from the link-response control symbol
SPRUE13A – September 2006 Serial RapidIO (SRIO) 201
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