Texas Instruments TMS320TCI648x - Manual (Page 124)

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5.12 Packet Forwarding Register n for 8-Bit Device IDs (PF_8B_CNTLn)
SRIO Registers
There are four of these registers (see Table 54 ). The general form of a packet forwarding register for
16-bit DeviceIDs is shown in Figure 73 and described in Table 55 . For additiona programming information
see Section 2.3.15 and and Section 2.3.15.3 .
Table 54. PF_8B_CNTL Registers
Register Address Offset
PF_8B_CNTL0 0094h
PF_8B_CNTL1 009Ch
PF_8B_CNTL2 00A4h
PF_8B_CNTL3 00ACh
Figure 73. Packet Forwarding Register n for 8-Bit Device IDs (PF_8B_CNTLn)
31 18 17 16
OUT_BOUND_
Reserved
PORT
R-0 R/W-3
15 8
8BIT_DEVID_UP_BOUND
R/W-FFh
7 0
8BIT_DEVID_LOW_BOUND
R/W-FFh
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 55. Packet Forwarding Register n for 8-Bit DeviceIDs (PF_8B_CNTLn) Field Descriptions
Bit Field Value Description
31–18 Reserved 0 Reserved
17–16 OUT_BOUND_PORT 0–3 Output port number for packets whose DestID falls within the 8-bit or
16-bit range for this table entry.
15–8 8BIT_DEVID_UP_BOUND 00h–FFh Upper 8-bit DeviceID boundary. DestID above this range cannot use
the table entry.
7–0 8BIT_DEVID_LOW_BOUND 00h–FFh Lower 8-bit DeviceID boundary. DestID lower than this number cannot
use the table entry.
Serial RapidIO (SRIO) 124 SPRUE13A – September 2006
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