Texas Instruments TMS320TCI648x - Manual (Page 123)

www.ti.com
5.11 Packet Forwarding Register n for 16-Bit Device IDs (PF_16B_CNTLn)
SRIO Registers
There are four of these registers (see Table 52 ). The general form of a packet forwarding register for
16-bit DeviceIDs is shown in Figure 72 and described in Table 53 . For additional programming
information, see Section 2.3.15 and Section 2.3.15.3 .
Table 52. PF_16B_CNTL Registers
Register Address Offset
PF_16B_CNTL0 0090h
PF_16B_CNTL1 0098h
PF_16B_CNTL2 00A0h
PF_16B_CNTL3 00A8h
Figure 72. Packet Forwarding Register n for 16-Bit Device IDs (PF_16B_CNTLn)
31 16 15 0
16BIT_DEVID_UP_BOUND 16BIT_DEVID_LOW_BOUND
R/W-FFFFh R/W-FFFFh
LEGEND: R/W = Read/Write; -n = Value after reset
Table 53. Packet Forwarding Register n for 16-Bit DeviceIDs (PF_16B_CNTLn) Field Descriptions
Bit Field Value Description
31–16 16BIT_DEVID_UP_BOUND 0000h–FFFFh Upper 16-bit DeviceID boundary. DestID above this range
cannot use the table entry.
15–0 16BIT_DEVID_LOW_BOUND 0000h–FFFFh Lower 16-bit DeviceID boundary. DestID lower than this
number cannot use the table entry.
SPRUE13A – September 2006 Serial RapidIO (SRIO) 123
Submit Documentation Feedback