Texas Instruments TMS320TCI648x - Manual (Page 197)

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5.66 Port Link Time-Out Control CSR (SP_LT_CTL)
SRIO Registers
The port link time-out control CSR (SP_LT_CTL) is shown in Figure 129 and described in Table 137 .
Figure 129. Port Link Time-Out Control CSR (SP_LT_CTL) - Address Offset 1120h
31
TIMEOUT_VALUE
R/W-FFFFFFh
8 7 0
TIMEOUT_VALUE Reserved
R/W-FFFFFFh R-00h
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 137. Port Link Timeout Control CSR (SP_LT_CTL) Field Descriptions
Bit Field Value Description
31–8 TIMEOUT_VALUE Timeout value for all ports on the device. This timeout is for link events
such as sending a packet to receiving the corresponding ACK. Max
value represents 3-6 seconds. Timeout duration = 205 ns * Timeout
Value; where Timeout value is the decimal representation of this register
value.
FFFFFFh 3.4 s
0FFFFFh 215 ms
00FFFFh 13.4 ms
000FFFh 839.5
µ
s
0000FFh 52.3 µ s
00000Fh 3.1
µ
s
000001h 205 ns for simulation only
000000h Timer disabled
7–0 Reserved 00h These read-only bits return 0s when read.
SPRUE13A – September 2006 Serial RapidIO (SRIO) 197
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