Texas Instruments TMS320TCI648x - Manual (Page 42)

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2.3.3.3 Direct I/O RX Operation
SRIO Functional Description
Segmentation:
The LSU handles two types of segmentation of outbound requests. The first type is when the Byte_Count
of Read/Write requests exceeds 256 bytes (up to 4K bytes). The second type is when Read/Write request
RapidIO address is non-64-bit aligned. In both cases, the outgoing request is broken up into multiple
RapidIO request packets. For example, assume that the CPU wants to perform a 1K-byte store operation
to an external RapidIO device. After setting up the LSU registers, the CPU performs one write to the
LSUn_REG5 register. The peripheral hardware then segments the store operation into four RapidIO write
packets of 256 bytes each, and calculates the 64-bit-aligned RapidIO address, WRSIZE, and WDPTR as
required for each packet. This example requires four outbound handles to be assigned and four DMA
transmit requests. The LSU registers cannot be released until all posted request packets are passed to
the TX FIFOs. Alternatively, for non-posted operations, such as CPU loads, all packet responses must be
received before the LSU registers are released.
Response packets are always type 13 RapidIO packets. All response packets with transaction types not
equal to 0001b are routed to the LSU block sequentially in order of reception. These packets may have a
payload, depending on the type of corresponding request packet that was originally sent. Due to the
nature of RapidIO switch fabric systems, response packets can arrive in any order. The data payload, if
any, and header data is moved from the RX FIFO to the shared RX buffer. The targetTID field of the
packet is examined to determine which core and corresponding set of registers are waiting for the
response. Remember, there can be only one outstanding request per core. Any payload data is moved
from the shared RX buffer into memory through normal DMA bus operations.
Registers for all non-posted operations should only be held for a finite amount of time to avoid blocking
resources when a request or response packet is somehow lost in the switch fabric. This time correlates to
the 24-bit Port Response Time-out Control CSR value discussed in sections 5.10.1 and 6.1.2.4 of the
RapidIO Physical Layer 1x/4x LP-Serial Specification. If the time expires, control/command register
resources should be released, and an error is logged in the error-management RapidIO registers. The
RapidIO Interconnect Specification states that the maximum time interval (all 1s) is between 3 and 6
seconds. A logical layer timeout occurs if the response packet is not received before a countdown timer
(initialized to this CSR value) reaches zero.
Each outstanding packet response timer requires a 4-bit register. The register is loaded with the current
timecode when the transaction is sent. The timecode comes from a 4 bit counter associated with the 24 bit
down counter that continually counts down and is re-loaded with the value of SP_RT_CTL (Address offset
1124h) when it reaches 0. Each time the timecode changes, a 4-bit compare is done to the register. If the
register becomes equal to the timecode again, without a response being seen, then the transaction has
timed out. Essentially, instead of the 24-bit value representing the period of the response timer, the period
is now defined as P = (2^24 x 16)/F. This means the countdown timer frequency needs to be 44.7 –
89.5Mhz for a 6 – 3 second response timeout. Because the needed timer frequency is derived from the
DMA bus clock (which is device dependent), the hardware supports a programmable configuration register
field to properly scale the clock frequency. This configuration register field is described in the Peripheral
Setting Control register (Address offset 0020h).
If a response packet indicates ERROR status, the Load/Store module notifies the CPU by generating an
error interrupt for the pending non-posted transaction. If the response has completed successfully, and the
Interrupt Req bit is set in the control register, the module generates a CPU servicing interrupt to notify the
CPU that the response is available. The control/command registers can be released as soon as the
response packet is received by the logical layer. The hardware is not responsible for attempting a
retransmission of the non-posted transaction.
If a Doorbell response packet indicates Retry status, the Load/Store module notifies the CPU by
generating an interrupt. The control/command registers can be released as soon as the response packet
is received by the logical layer. The hardware is not responsible for attempting retransmission of the
Doorbell transaction.
42 Serial RapidIO (SRIO) SPRUE13A – September 2006
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