Texas Instruments TMS320TCI648x - Manual (Page 95)

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4.4.1.2 LSU Interrupt Condition Routing Registers
Interrupt Conditions
Figure 56. TX CPPI Interrupt Condition Routing Registers
TX CPPI Interrupt Condition Routing Register (TX_CPPI_ICRR) (Address Offset 02D0h)
31 28 27 24 23 20 19 16
ICR7 ICR6 ICR5 ICR4
R/W-0000 R/W-0000 R/W-0000 R/W-0000
15 12 11 8 7 4 3 0
ICR3 ICR2 ICR1 ICR0
R/W-0000 R/W-0000 R/W-0000 R/W-0000
TX CPPI Interrupt Condition Routing Register 2 (TX_CPPI_ICRR2) (Address Offset 02D4h)
31 28 27 24 23 20 19 16
ICR15 ICR14 ICR13 ICR12
R/W-0000 R/W-0000 R/W-0000 R/W-0000
15 12 11 8 7 4 3 0
ICR11 ICR10 ICR9 ICR8
R/W-0000 R/W-0000 R/W-0000 R/W-0000
LEGEND: R/W = Read/Write; -n = Value after reset
Figure 57 shows the ICRRs for the LSU interrupt requests. These registers route LSU interrupt requests to
interrupt destinations. For example, if ICS4 = 1 in LSU_ICSR and ICR4 = 0000b in LSU_ICRR0, LSU1
has generated a transaction-timeout interrupt request, and that request is routed to interrupt destination 0.
SPRUE13A – September 2006 Serial RapidIO (SRIO) 95
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