ARM Cortex R4F - Manual (Page 176)

Events and Performance Monitor
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 6-12
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If you attempt to use the SWINCR Register to increment a performance monitor count register
when the counter event is set to a value other than
0x00
the result is Unpredictable.
Figure 6-5 shows the bit arrangement for the SWINCR Register.
Figure 6-5 SWINCR Register format
Table 6-6 shows how the bit values correspond with the SWINCR Register.
To access the SWINCR Register, read or write CP15 with:
MRC p15, 0, <Rd>, c9, c12, 4 ; Read SWINCR Register
MCR p15, 0, <Rd>, c9, c12, 4 ; Write SWINCR Register
6.3.6 c9, Performance Counter Selection Register
The Performance Counter SELection (PMNXSEL) Register selects a Performance Monitor
Count Register. It determines which count register is accessed or controlled by accesses to the
Event Selection Register and the Performance Monitor Count Register.
The PMNXSEL Register is:
• A read/write register
• Always accessible in Privileged mode. The USEREN Register determines accessibility in
User mode, see c9, User Enable Register on page 6-15.
Figure 6-6 shows the bit arrangement for the PMNXSEL Register.
Figure 6-6 PMNXSEL Register format
31 3 2 1 0
Reserved
P2
P1
P0
Performance monitor counters
software increment bits
Table 6-6 SWINCR Register bit functions
Bits Field Function
[31:3] Reserved RAZ on reads, SBZP on writes
[2] P2 Increment Counter 2
[1] P1 Increment Counter 1
[0] P0 Increment Counter 0
SEL
31 4 0
Reserved
5