ARM Cortex R4F - Manual (Page 232)

Level One Memory System
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8.8 Error detection events
The processor generates a number of events related to the internal error detection and correction
schemes in the TCMs and caches. For more information, see Table 6-1 on page 6-2. This section
describes:
•
TCM error events
• Instruction-cache error events
• Data-cache error events
• Events and the CFLR.
8.8.1 TCM error events
TCM parity and ECC error events are only signaled for TCM reads, although this includes the
read-modify-write sequence performed for some stores. Most errors detected by the internal
parity or ECC logic are signaled twice:
•
once on a TCM-centric event
• once on a processor-centric event.
The TCM-centric events consist of two events per TCM port, one for fatal, that is, 2-bit ECC or
parity errors and one for correctable, that is, 1-bit ECC errors. These events are generated three
clock cycles after the data read cycle. Consequently, these events are sometimes signaled on
speculative TCM reads, such as instructions which are prefetched but never executed because
of a branch earlier in the instruction sequence.
Note
When an external error is signaled on a TCM access, the TCM-centric events are still generated
as appropriate, based on the data returned, as if no external error had been signaled.
The processor-centric TCM events are only signaled for errors in data that would have otherwise
been used by the processor. Errors on speculative reads never generate these errors. They consist
of fatal and correctable events for:
•
the prefetch unit, to signal errors on instruction fetches
• the load/store unit, to signal errors on data accesses
• the AXI slave interface, to signal errors on DMA accesses.
8.8.2 Instruction-cache error events
All parity and ECC errors are correctable in the i-cache. Therefore there are only two events, to
indicate when an error is detected in a read from the tag RAM, or from the data RAM. These
events are only signaled for non-speculative instruction fetches and certain cache maintenance
operations. See Cache error detection and correction on page 8-20.
8.8.3 Data-cache error events
The d-cache can generate fatal and correctable errors, and therefore has four events, one for each
type of error in the data RAM and in the tag or dirty RAMs. These events are only signaled for
non-speculative data accesses, cache line evictions, and certain cache maintenance operations.
See Cache error detection and correction on page 8-20.
8.8.4 Events and the CFLR
The Correctable Fault Location Register (CFLR) records the location of the last correctable
error detected on a non-speculative access. See Correctable Fault Location Register on
page 4-70 for more information. Every correctable error that is recorded in the CFLR also