ARM Cortex R4F - Manual (Page 29)

Introduction
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1.3.6 Debug
The processor has a CoreSight compliant Advanced Peripheral Bus version 3 (APBv3) debug
interface. This permits system access to debug resources, for example, the setting of
watchpoints and breakpoints.
The processor provides extensive support for real-time debug and performance profiling.
The following sections give an overview of debug:
•
System performance monitoring
• ETM interface
• Real-time debug facilities.
System performance monitoring
This is a group of counters that you can configure to monitor the operation of the processor and
memory system. For more information, see About the PMU on page 6-6.
ETM interface
The Embedded Trace Macrocell (ETM) interface enables you to connect an external ETM unit
to the processor for real-time code tracing of the core in an embedded system.
The ETM interface collects various processor signals and drives these signals from the
processor. The interface is unidirectional and runs at the full speed of the processor. The ETM
interface connects directly to the external ETM unit without any additional glue logic. You can
disable the ETM interface for power saving. For more information, see the CoreSight ETM-R4
Technical Reference Manual.
Real-time debug facilities
The processor contains an EmbeddedICE-RT logic unit to provide real-time debug facilities. It
has:
•
up to eight breakpoints
• up to eight watchpoints
• a Debug Communications Channel (DCC).
Note
The number of breakpoints and watchpoints is configured during implementation, see
Configurable options on page 1-13.
The EmbeddedICE-RT logic monitors the internal address and data buses. You access the
EmbeddedICE-RT logic through a memory-mapped APB interface.
The processor implements the ARMv7 Debug architecture, including the extensions of the
architecture to support CoreSight.
To get full access to the processor debug capability, you can access the debug register map
through the APBv3 slave port. See Chapter 11 Debug for more information on debug.