ARM Cortex R4F - Manual (Page 360)

Integration Test Registers
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 13-6
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This section describes:
•
Using the Integration Test Registers
• Performing integration testing
• ITETMIF Register (ETM interface) on page 13-7
• ITMISCOUT Register (Miscellaneous Outputs) on page 13-8
• ITMISCIN Register (Miscellaneous Inputs) on page 13-8
• Integration Mode Control Register (ITCTRL) on page 13-9
13.4.1 Using the Integration Test Registers
When bit [0] of the Integration Mode Control Register (ITCTRL) is set to b1:
• Values written to the write-only Integration Test Registers map onto the specified outputs
of the macrocell. For example, writing
b1
to ITMISCOUT[0] causes DBGACK to be
asserted HIGH.
• Values read from the read-only Integration Test Registers correspond to the values of the
specified inputs of the macrocell. For example, if you read ITMISCIN[9:8] you obtain
the value of ETMEXTOUT[1:0].
13.4.2 Performing integration testing
When you perform integration testing or topology detection:
• You must ensure that the other ETM interface signals cannot change value during
integration testing.
• ARM strongly recommends that the processor is halted while in debug state, because
toggling input and output pins might have an unwanted effect on the operation of the
processor. You must not set the ITCTRL Register until the processor has halted.
When the ITCTRL Register is set, the ETM interface stops trace output, and outputs the
data written into the relevant integration registers.
After you perform integration testing or topology detection, that is, the Integration Mode
Control Register has been set, the system must be reset. This is because the signals that are
toggled can have an unwanted effect on connected devices.
Table 13-3 Input signals that can be read by the Integration Test Registers
Signal Register Bit Register description
DBGRESTART ITMISCIN [11] See ITMISCIN Register (Miscellaneous Inputs) on page 13-8
ETMEXTOUT[1:0] ITMISCIN [9:8]
nETMWFIREADY ITMISCIN [5]
nIRQ ITMISCIN [2]
nFIQ ITMISCIN [1]
EDBGRQ ITMISCIN [0]