ARM Cortex R4F - Manual (Page 392)

Cycle Timings and Interlock Behavior
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-28
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14.18 Miscellaneous instructions
Table 14-23 shows the cycle timing behavior for If-Then (IT) and No OPeration (NOP)
instructions.
The
DBG
,
PLI
,
SEV
,
WFE
, and
YIELD
instructions are all treated the same as
NOP
, and so have the same
cycle timing behavior.
The
WFI
instruction stalls the pipeline for a variable number of cycles, depending on the current
state of the memory system.
Table 14-23 IT and NOP instructions cycle timing behavior
Example instructions Cycles Early Reg Late Reg Result latency Comments
IT{<v>{<w>{<z>}}} <cond> 1 - - - -
NOP 1 - - - -