ARM Cortex R4F - Manual (Page 423)

Processor Signal Descriptions
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A.5.2 AXI master port error detection signals
Table A-5 shows the AXI master port error detection signals. these signals are only generated if
the processor is configured to include AXI bus parity. See Configurable options on page 1-13
for more information.
A.5.3 AXI slave port
Table A-6 shows the AXI slave port signals for the L2 interface. With the exception of the
ACLKENS, all signals are only sampled or driven on CLKIN edges when ACLKENS is
asserted, see AXI interface clocking on page 3-9 for more information.
ARUSERM[4:0] Output CLKIN Provides decode information for the read address channel. See
Table 9-3 on page 9-5 for information about the encoding of this
signal.
ARVALIDM Output CLKIN Indicates address and control are valid.
Read Data Channel
RDATAM[63:0] Input CLKIN Read Data.
RIDM[3:0] Input CLKIN The identification tag for the read data group of signals.
RLASTM Input CLKIN Indicates the last transfer in a read burst.
RREADYM Output CLKIN Read ready signal indicating that the bus master can accept read
data and response information.
RRESPM[1:0] Input CLKIN Read response.
RVALIDM Input CLKIN Indicates that read data is available.
Table A-4 AXI master port signals for the L2 interface (continued)
Signal Direction Clocking Description
Table A-5 AXI master port error detection signals
Signal Direction Clocking Description
AWPARITYM Output CLKIN Parity bit for write address channel
WPARITYM Output CLKIN Parity bit for write data channel
BPARITYM Input CLKIN Parity bit for write response channel
ARPARITYM Output CLKIN Parity bit for read address channel
RPARITYM Input CLKIN Parity bit for read data channel
AXIMPARERR[1:0] Output CLKIN Parity error indication for read data (bit [1]) and write response
(bit[0]) channels
Table A-6 AXI slave port signals for the L2 interface
Signal Direction Clocking Description
ACLKENS Input CLKIN Clock enable for the AXI slave port.
Write Address Channel
AWADDRS[22:0] Input CLKIN Transfer start address.