ARM Cortex R4F - Manual (Page 46)

Introduction
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Table 1-3 shows the mappings between these various numbers, for all releases.
1.11.2 Architectural information
The ARM Architecture includes a number of registers that identify the version of the
architecture and some of the architectural features that a processor implements. Chapter 4
System Control Coprocessor describes the values that the processor implements for the fields in
these registers. For details of the possible values and their meanings for these fields, see the
ARM Architecture Reference Manual.
Table 1-3 ID values for different product versions
ID value r0p0 r0p1 r0p2 r0p3 r1p0 r1p1 r1p2 r1p3
Variant field, Main ID Register 0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1
Revision field, Main ID Register 0x0 0x1 0x2 0x3 0x0 0x1 0x2 0x3
Variant field, Debug ID Register 0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1
Revision field, Debug ID Register 0x0 0x1 0x2 0x3 0x0 0x1 0x2 0x3
Revision number, Peripheral ID Registers
0x0 0x1 0x2 0x5 0x3 0x4 0x6 0x7
Revision number, FPSID Register - - - - 0x3 0x4 0x6 0x7