Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 112)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
112
Power-On/Power-Fail Reset
The DS80C400 incorporates an internal voltage reference that holds the CPU in the power-on reset state if V
CC1
is below V
RST1
or V
CC3
is below V
RST3
. Once both supplies have risen above the respective thresholds (i.e., V
CC1
> V
RST1
and V
CC3
> V
RST3
), the microcon-
troller then restarts the oscillation of the external crystal and counts 65,536 clock cycles. This helps the system maintain reliable oper-
ation by permitting operation only when both supply voltages are in a known good state.
The CPU exits the reset condition once the above conditions are met. This happens automatically, needing no external components or
action. Execution begins at the standard reset vector address of 000000h. Software can determine when a power-on reset has occurred
using the power-on reset flag (POR) located at WDCON.6. The POR flag is set only by a power-on reset and is unaffected by other reset
sources. Since all resets cause a vector to location 000000h, software can read the POR flag to assess whether power failure was the rea-
son for the reset. If the POR bit is intended to identify a power-on reset, software must clear the POR bit after reading it. This ability to dis-
tinguish a power-on reset from other reset sources allows different processing routines in accordance to the reset source.
When either power supply fails (V CC1 < V RST1 or V CC3 < V RST3 ), the power monitoring circuitry invokes the reset state again. This reset con-
dition remains while the power is below the threshold. When the power supply rises above the reset threshold, a full power-on reset is per-
formed. Thus, a brownout that causes one of the supplies to drop below the specified minimum threshold appears the same as a power-up.
Watchdog Timer Reset
The watchdog timer is a free-running timer with a programmable interval. The watchdog supervises CPU operation by requiring soft-
ware to reset it before the timeout expires. If the timer is enabled and software fails to clear it before this interval expires, a watchdog
interrupt can be generated, if enabled. Furthermore, if the watchdog reset function has been enabled, the CPU can be placed into a
reset state. The reset state is maintained for two machine cycles. Once the reset is removed, the software resumes execution at
000000h.
The watchdog timer is fully described in Section 11 of the High-Speed Microcontroller User’s Guide. Software can determine that a
watchdog timeout was the reason for the reset by using the watchdog timer reset flag (WTRF) located at WDCON.2. Hardware sets
this bit to a logic 1 if the watchdog timer generates a reset. If a watchdog timer reset occurs, software should clear this flag manually.
This allows software to detect the event if it occurs again.
External Reset
If the RST input is taken to a logic 1, the CPU is forced into a reset state. This does not occur instantaneously, as the condition must
be detected and then clocked into the microcontroller. It requires between one and two machine cycles to detect and invoke the reset
state. Thus, the reset is a synchronous operation and the internal CPU clock (derived from the external crystal oscillator or the ring
oscillator) must be active to detect an external reset.
Once the reset state is invoked, it is maintained as long as RST = 1. When the RST is removed, the CPU exits the reset state within one
to two machine cycles and begins execution at address 000000h. All registers default to their reset state. There is no flag to indicate
that an external reset was applied. However, since the other three sources have associated flags, the RST pin is the default source
when neither POR, WTRF, nor OFDF is set.
If an RST is applied while the processor is in the stop mode, the scenario changes slightly. As mentioned above, the reset is synchro-
nous and requires a clock to be running. Since the stop mode stops all clocks, the RST initially causes the oscillator to begin running
and forces the program counter to 000000h. Rather than the two-machine cycle delay described above, the processor applies the full
power-on delay (65536 clocks) to allow the oscillator to stabilize.
Oscillator Fail-Detect Reset
Most members of the high-speed microcontroller family contain a watchdog timer. The intent of this timer is to force the processor into
a known good state (reset) if it ever entered a runaway situation where it was not executing code properly. This is a very powerful fea-
ture but could be made stronger with a simple addition. Since the watchdog timer clock was derived from the main crystal oscillator,
it is possible (though very unlikely) that the oscillator could fail (stop), leaving the processor in an undesirable state. Since the watch-
dog timer runs from the same clock, the timer would stop counting, which would prevent a watchdog timeout and the generation of a
watchdog reset. This possibility is eliminated in the DS80C400 by the inclusion of an oscillator fail-detection circuit. When enabled, this
circuit causes the processor to be reset if the oscillator frequency falls below 100kHz. This puts the processor into a known good state,
regardless of the watchdog timer, if the main crystal oscillator should ever fail. Although the oscillator has failed when this reset occurs,
the CPU is clocked into the normal reset state by other internal clocks.
The oscillator fail-detect feature is enabled by setting the OFDE (PCON.4) bit with software. This bit can be modified at any time. When
an oscillator fail detection occurs, the flag OFDF (PCON.5) bit is set by hardware when the processor enters reset. This bit must be
cleared by software. The oscillator fail-detection circuit is not active during the crystal-warmup period and is not triggered when the
oscillator is stopped upon entering stop mode.
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