Wire master data register (owmdr), B register (b), Slave address mask enable register 2 (saden2) – Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement User Manual
Page 89: Data pointer low register 2 (dpl2)
High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
89
7
6
5
4
3
2
1
0
SFR EFh
OWMDR.7
OWMDR.6
OWMDR.5
OWMDR.4
OWMDR.3
OWMDR.2
OWMDR.1
OWMDR.0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
7
6
5
4
3
2
1
0
SFR F1h
SADEN2.7
SADEN2.6
SADEN2.5
SADEN2.4
SADEN2.3
SADEN2.2
SADEN2.1
SADEN2.0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
7
6
5
4
3
2
1
0
SFR F0h
B.7
B.6
B.5
B.4
B.3
B.2
B.1
B.0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
7
6
5
4
3
2
1
0
SFR F2h
DPL2.7
DPL2.6
DPL2.5
DPL2.4
DPL2.3
DPL2.2
DPL2.1
DPL2.0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
1-Wire Master Data Register (OWMDR)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
B Register (B)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
Slave Address Mask Enable Register 2 (SADEN2)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
Data Pointer Low Register 2 (DPL2)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
OWMDR.7–0
Bits 7–0
1-Wire master data register. This register contains the data value of the target register as selected by
the A2:A0 bits in the OWMAD SFR, when read to the OWMDR. A write to the OWMDR causes a write
access to the target register as selected by the A2:A0 bit in the OWMAD SFR and updates the target
register with the new data.
B.7–0
Bits 7–0
B register. This register serves as a second accumulator for certain arithmetic operations. It is func-
tionally identical to the B register found in the 80C32.
DPL2.7–0
Bits 7–0
Data pointer low byte 2. This register is the low byte of the auxiliary data pointer and contains the low-
order byte of the 24-bit data address.
SADEN2.7–0
Bits 7–0
Slave address mask enable register 2. This register is a mask enable when comparing serial port 2
addresses for automatic address recognition. When a bit is set in this register, the corresponding bit
location in the SADDR2 register is exactly compared with the incoming serial port 2 data to determine
if a receive interrupt should be generated. When a bit in this register is cleared, the corresponding bit
in the SADDR2 register becomes a “don’t care” and is not compared against the incoming data. All
incoming data generates a receive interrupt when this register is cleared.
Maxim Integrated