Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 17)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
17
Register Map
The register map is separate from the program and data memory areas mentioned above. A separate class of instructions is used to
access the registers. There are 256 potential register location values. In practice, the high-speed microcontroller has 256 bytes of
scratchpad RAM and up to 128 SFRs. This is possible since the upper 128 scratchpad RAM locations can only be accessed indirectly.
That is, the contents of a working register, described later, designate the RAM location. Thus, a direct reference to one of the upper
128 locations must be an SFR access. Direct RAM is reached at locations 0 to 7Fh (0–127). SFRs are accessed directly between 80h
and FFh (128–255). The RAM locations between 128 and 255 can be reached through an indirect reference to those locations.
Scratchpad RAM is available for general-purpose data storage. It is commonly used in place of off-chip RAM when the total data con-
tents are small. When off-chip RAM is needed, the scratchpad area still provides the fastest general-purpose access. Within the 256
bytes of RAM, there are several special-purpose areas, which are described as follows.
Bit-Addressable Locations
In addition to direct register access, some individual bits in both the RAM and SFR area are also accessible. In the scratchpad RAM
area, registers 20h to 2Fh are bit addressable. This provides 128 (16 x 8) individual bits available to software. The type of instruction
distinguishes a bit access from a full register access. In the SFR area, any register location ending in a 0 or 8 is bit addressable.
Working Registers
As part of the lower 128 bytes of RAM, there are four banks of general-purpose working registers, each bank containing registers
R0–R7. The bank is selected by bits in the program status word register. Since there are four banks, the currently selected bank is used
by any instruction using R0–R7. This allows software to change context by switching banks. The working registers also allow their con-
tents to be used for indirect addressing of the upper 128 bytes of RAM. Thus, an instruction can designate the value stored in R0, for
example, to address the upper RAM. This value might be the result of another calculation.
Stack
Another use of the scratchpad area is for the programmer’s stack. This area is selected using the stack pointer (SP: 81h) SFR.
Whenever a call or interrupt is invoked, the return address is placed on the stack. It is also available to the programmer for variables,
etc. The stack pointer defaults to 07h on reset, but can be relocated as needed. A convenient location would be the upper RAM area
(> 7Fh), since this is only available indirectly. The SP points to the last used value. Therefore, the next value placed on the stack is put
at SP + 1. Each PUSH or CALL increments the SP by the appropriate value. Each POP or RET decrements, as well.
The DS80C400 supports an optional 10-bit (1kB) stack. This greatly increases programming efficiency and allows the device to sup-
port large programs. When enabled by setting the stack address (SA) bit in the ACON register, 1kB of the internal SRAM is allocated
for use as the stack. The 10-bit address is formed by concatenating the lower 2 bits of the extended stack pointer (ESP: 9Bh) and the
8-bit stack pointer (SP: 81h). The exact address of the 1kB is dependent on the setting of the IDM1-0 bits.
Special-Function Register Maps
Most of the unique features of the high-speed microcontroller family are controlled by bits in SFRs located in unused locations in the
8052 SFR map. This allows for increased functionality, while maintaining complete instruction set compatibility. The SFRs reside in reg-
ister locations 80h–FFh and are accessed using direct addressing. SFRs that end in 0h or 8h are bit addressable.
The Special Function Register Map table indicates the names and locations of the SFRs used by the DS80C400. The Special Function
Register Location table shows individual bits in those registers. Bits protected by the timed-access function are shaded. The Special
Function Register Reset Values table indicates the reset state of all SFR bits. Following these tables is a complete description of
DS80C400 SFRs that are new to the 8051 architecture or have new or modified functionality.
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