Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 33)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
33
External Interrupt Flag (EXIF)
7 6 5 4 3 2 1 0
SFR 91h IE5 IE4 IE3 IE2 CKRY RGMD RGSL BGS
RW-0 RW-0 RW-0 RW-0 R-* R-* RW-* RT-0
R = Unrestricted read, W = Unrestricted write, T = Timed-access write only, -n = Value after reset, * = Bits 1, 2 and 3 are cleared to 000b by a power-on reset, but are
unchanged by all other forms of reset.
IE5
Bit 7
IE4
Bit 6
IE3
Bit 5
IE2
Bit 4
CKRY
Bit 3
RGMD
Bit 2
RGSL
Bit 1
BGS
Bit 0
External interrupt 5 flag. This bit is set when a falling edge is detected on INT5. This bit must be
cleared manually by software. Setting this bit in software causes an interrupt if enabled. Please note that,
when the EOWMI bit internal to the 1-Wire bus master is set to 1, the IE5 flag serves as the 1-Wire bus
master interrupt flag.
External interrupt 4 flag. This bit is set when a rising edge is detected on INT4. This bit must be cleared
manually by software. Setting this bit in software causes an interrupt, if enabled.
External interrupt 3 flag. This bit is set when a falling edge is detected on INT3. This bit must be
cleared manually by software. Setting this bit in software causes an interrupt, if enabled.
External interrupt 2 flag. This bit is set when a rising edge is detected on INT2. This bit must be cleared
manually by software. Setting this bit in software causes an interrupt, if enabled.
Clock ready. The CKRY bit indicates the status of the startup period delay used by the crystal oscilla-
tor and the crystal clock multiplier warmup period. CKRY = 0 indicates the startup delay is still count-
ing. When the CKRY = 1, the counter has completed. This bit is cleared each time the CTM bit in the
PMR register is changed from low to high to start the crystal multiplier. Once the CKRY is set, the lock-
out is removed on the CD1, CD0 bits to select the multiplied crystal clock as a system clock source. This
status bit is also cleared each time the crystal oscillator is restarted when exiting stop mode.
Ring mode status. This bit indicates the current clock source for the device. This bit is cleared to 0 after
a power-on reset, and is unchanged by all other forms of reset.
0 = Device is operating from the external crystal or oscillator.
1 = Device is operating from the ring oscillator.
Ring oscillator select. This bit selects the clock source following a resume from stop mode. Using the
ring oscillator to resume from stop mode allows almost instantaneous startup. This bit is cleared to 0
after a power-on reset and is unchanged by all other forms of reset. The state of this bit is undefined on
devices that do not incorporate a ring oscillator.
0 = The device holds operation until the crystal oscillator has warmed up.
1 = The device begins operating from the ring oscillator and, when the crystal warmup is complete, it
switches to the external clock source or oscillator.
Bandgap select. This bit enables/disables the bandgap reference during stop mode. Disabling the
bandgap reference provides significant power savings in stop mode, but sacrifices the ability to perform
a power-fail interrupt or power-fail reset while stopped. This bit can only be modified with a timed access
procedure.
0 = The bandgap reference is disabled in stop mode, but functions during normal operation.
1 = The bandgap reference operates in stop mode.
Maxim Integrated