Can 0 receive-error register (c0re) – Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement User Manual
Page 54
High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
54
CAN 0 Receive-Error Register (C0RE)
The following are the values of the INTIN7–0 bits for each interrupt source along with the respective pri-
ority of each.
INTERRUPT
SOURCE
INTIN7–0
HEX VALUE
INTERRUPT
PRIORITY
No pending interrupt
00
N/A
CAN 0 status register
01
Highest = 1
Message 15
02
2
Message 1
03
3
Message 2
04
4
Message 3
05
5
Message 4
06
6
Message 5
07
7
Message 6
08
8
Message 7
09
9
Message 8
0A
10
Message 9
0B
11
Message 10
0C
12
Message 11
0D
13
Message 12
0E
14
Message 13
0F
15
Message 14
10
Lowest = 16
7
6
5
4
3
2
1
0
SFR A7h
CORE.7
CORE.6
CORE.5
CORE.4
CORE.3
CORE.2
CORE.1
CORE.0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
This SFR is not present on the DS80C411.
C0RE.7–0
Bits 7–0
CAN 0 receive-error register. The CAN 0 receive-error register provides a means of reading the CAN
0 receive-error counter. New values can be loaded into the receive error counter through the CAN 0
transmit error register. CORE is cleared to a 00 hex following all hardware resets and software resets
enabled by the CRST bit in the CAN 0 control register.
Maxim Integrated