Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 48)

CAN 0 Status Register (C0S)
High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
48
C0S.7–0
Bits 7-0
BSS
Bit 7
EC96/128
Bit 6
CAN 0 status register. The first three bits, BSS, EC96, and WKS, and the last 3 bits, ER2–ER0, in the
CAN status register are read only by the microcontroller. The CAN processor sets or clears these flags
(and interrupt sources) as defined by the system aspects associated with each bit. A CAN status reg-
ister read clears the internal status-change interrupt flag. Unlike RXS and TXS, however, the individual
mechanisms that set the ER2, ER0, BSS, EC96, and WKS bits do not reoccur without first being removed
by the CAN processor. As a result, a new (0 ≥ 1) change by BSS, EC96, or (1 ≥ 0) change by WKS is
required to set a new internal status change interrupt flag through these bits. In a similar fashion, a read
of the CAN status register (which automatically sets ER2–ER0 to 111), followed by a new transmit or
receive error, is required to set a new internal status change interrupt flag. If any one of these bits
changes state from a previous 0 to a 1 (other than WKS, which changes from a 1 to a 0) and STIE is set
to 1 with no other interrupt pending, the INTIN vector in the CAN interrupt register is set to 01 hex. If TXS
or RXS is set to a 1 and a second message is successfully transmitted or received, and STIE is set to 1
while no other interrupt is pending, the INTIN vector in the CAN interrupt register is also set to 01 hex.
If ER[2:0] changes from either a 000 or 111 binary state to any state other than 000 or 111, the INTIN
vector in the CAN interrupt register is also set to 01 hex. This issues a status change interrupt request
if at least one of the following conditions is valid and no other interrupt is pending.
CAN 0 bus status. (Read only.) The BSS bit reflects the current status of the CAN 0 bus. When BSS =
1, the CAN 0 bus is disabled (bus off) and is not capable of receiving or transmitting messages. This
condition is the result of the transmit-error counter reaching a count of 256. When the CAN processor
detects an error count of 256, the CAN processor automatically sets BSS = 1 and clears SWINT = 0.
BSS is cleared to a 0 to enable CAN 0 bus activity when the CAN processor completes both the bus-off
recovery (128kB x 11 consecutive recessive bits) and the power-up sequence (11 consecutive reces-
sive bits). Once the CAN processor has completed this relationship, it sets SWINT = 1 and enters into
the software initialization state. Once the microcontroller has cleared SWINT to a 0, the CAN processor
is enabled to transmit and receive messages. BSS is set to a 1 whenever the transmit error counter for
CAN 0 reaches the 256 limit. When BSS = 0, the CAN 0 bus is enabled to receive or transmit messages.
A change in the state of BSS from a previous 0 to a 1 generates an interrupt if the ERIE, C0IE, and IE
SFR register bits are set. All microcontroller writes to the SWINT bit are disabled when BSS = 1. Both the
transmit- and receive-error counters are cleared to 00 hex when the bus-off condition is cleared by the
CAN module and BSS is cleared to 0.
CAN 0 error count greater than 96/128 status. (Read only.) The EC96/128 bit operates in one of two
modes. These two modes are determined by the state of the C0C.1 bit in the CAN 0 control register.
Following a system or CAN reset, the C0C.1 bit is cleared to a 0, which in turn enables the EC96 mode.
C0C.1 = 0, EC96/128 = EC96. In this mode, when EC96/128 = 1, the interrupt flag indicates that either
the CAN 0 transmit error counter or the CAN 0 receive error counter has exceeded an error count of 96,
an exceptional high number of errors. EC96/128 = 0 indicates that the current transmit error counter and
receive error counter both have an error count of less than 97. A change in the state of EC96/128 from
a previous 0 to a 1 generates an interrupt if the ERIE, C0IE, and IE SFR register bits are set. When C0C.1
is programmed to a 1, the EC96/128 bit is reconfigured into an EC128 bit flag mode.
C0C.1 = 1, EC96/128 = EC128. In this mode, when EC96/128 = 1, the interrupt flag indicates that either
the CAN 0 transmit error counter or the CAN 0 receive error counter has reached an error count of 128,
an exceptional number of errors. EC96/128 = 0 indicates that the current transmit error counter and
receive error counter both have an error count of less than 128. A change in the state of EC96/128 from
either a previous 0 to a 1 or from a previous 1 to a 0 generates an interrupt if the ERIE, C0IE and IE SFR
register bits are set.
7 6 5 4 3 2 1 0
SFR A4h BSS EC96/128 WKS RXS TXS ER2 ER1 ER0
R-0 R-0 R-0 RW-0 RW-0 RW-0 R-0 R-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
This SFR is not present on the DS80C411.
Maxim Integrated