Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 27)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
27
Power Control (PCON)
SMOD_0
Bit 7
SMOD0
Bit 6
OFDF
Bit 5
OFDE
Bit 4
GF1
Bit 3
GF0
Bit 2
STOP
Bit 1
IDLE
Bit 0
Serial port 0 baud-rate doubler enable. This bit enables/disables the serial baud-rate doubling
function for serial port 0.
0 = Serial port 0 baud rate is defined by the baud-rate generation equation.
1 = Serial port 0 baud rate is double that defined by the baud-rate generation equation.
Framing error detection enable. This bit selects the function of the SCON0.7 and SCON1.7, and
SCON2.7.
SMOD0 = 0: SCON0.7, SCON1.7, and SCON2.7 function as SM0 as defined for serial port control registers.
SMOD0 = 1: SCON0.7, SCON1.7, and SCON2.7 are converted to the framing error (FE) flag for the
respective serial port.
Oscillator fail-detect flag. When set, this bit indicates that the preceding reset was caused by the
detection of the crystal oscillator frequency falling below approximately 30kHz, if OFDE = 1. OFDF bit
must be cleared by software, and it is not altered by the crystal oscillator frequency falling below 30kHz
when OFDE = 0. OFDF is not set when the processor forces the crystal to stop operation by the stop
mode.
Oscillator fail-detect enable. When the OFDE = 1, a system reset is generated any time the crystal
oscillator frequency falls below approximately 30kHz. This bit does not force a reset when the oscillator
is stopped by the software-enabled stop mode, or if the crystal is stopped when the processor is run-
ning from the internal ring oscillator. When the OFDE bit is cleared to logic 0, no reset is issued when
the crystal falls below the 30kHz.
General-purpose user flag 1. This is a bit-addressable, general-purpose flag for software control.
General-purpose user flag 0. This is a bit-addressable, general-purpose flag for software control.
Stop mode select. Setting this bit stops program execution, halts the CPU oscillator and internal timers,
and places the CPU in a low-power mode. This bit is cleared and operation is resumed by
an external reset or execution of an enabled external interrupt. This bit is always read as 0. Setting
this bit while IDLE = 1 places the device in an undefined state. Setting this bit also clears the CTM
bit. This bit cannot be set while either CAN module is active, i.e., SWINT = CRST = PDE = 0. The fol-
lowing sequence should be used to activate Stop mode: (1) set (CRST or SWINT or PDE) = 1 for
both CANs, (2) clear all CAN bus activity bits for both CANs, (3) set STOP = 1.
Idle mode select. Setting this bit stops program execution, but leaves the CPU oscillator, timers, serial
ports, and interrupts active. This bit is cleared by a reset, or any of the external interrupts, and resumes
normal program execution.
7 6 5 4 3 2 1 0
SFR 87h SMOD_0 SMOD0 OFDF ODFE GF1 GF0 STOP IDLE
RW-0 RW-0 RW-0* RW-0 RW-0 RW-0 RW-0 RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset, * = See description
Maxim Integrated