Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 87)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
87
7 6 5 4 3 2 1 0
SFR E8h EPMIE C0IE EAIE EWDI EWPI ES2 ET3 EX2-5
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
7 6 5 4 3 2 1 0
SFR EAh MXAX.7 MXAX.6 MXAX.5 MXAX.4 MXAX.3 MXAX.2 MXAX.1 MXAX.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
Extended Interrupt Enable (EIE)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
MOVX Address Extended Register (MXAX)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
EPMIE
Bit 7
C0IE
Bit 6
EAIE
Bit 5
EWDI
Bit 4
EWPI
Bit 3
ES2
Bit 2
ET3
Bit 1
EX2-5
Bit 0
Ethernet power mode interrupt enable.
EPMIE = 1 enables the Ethernet power mode interrupt.
EPMIE = 0 disables the Ethernet power mode interrupt.
CAN 0 interrupt enable. C0IE = 1 enables a change in the CAN 0 status register to initiate an interrupt
if the corresponding ERIE or STIE bit in the CAN 0 control register is set. C0IE = 0 disables a change in
the CAN 0 status register from generating an interrupt. This bit does not exist in the DS80C411.
Ethernet activity interrupt enable. EAIE = 1 enables the Ethernet activity interrupt if the RIF or TIF bit
in the BCUC register is set. EAIE = 0 disables the generation of an interrupt.
Watchdog interrupt enable. Setting this bit to 1 enables interrupt requests generated by the watchdog
timer. Clearing this bit to 0 disables the interrupt requests by the watchdog timer.
Write-protected interrupt enable. Setting this bit to 1 enables interrupt requests generated by the WPIF
flag in the MCON2. Clearing this bit to 0 disables the write-protected interrupt request. This bit does not
exist in the DS80C410/411.
Serial port 2 interrupt enable. Setting this bit to 1 enables interrupt requests generated by the RI_2 or
TI_2 flags in SCON2. Clearing this bit to 0 disables serial port 2 interrupts.
Timer 3 interrupt enable. Setting this bit to 1 enables interrupts from timer 3 TF3 flag in T3CM. Clearing
this bit to 0 disables all timer 3 interrupts.
External interrupt 2-5 enable. Setting this bit to 1 enables interrupt requests generated by the IE2, IE3,
IE4, or IE5 flag in EXIF. Clearing this bit to 0 disables the external interrupt 2 to 5.
MXAX.7–0
Bits 7–0 MOVX address extended register. This register is used to provide the extended address byte to com-
plement the low byte address provided by the indirect addressing of the Ri register. Using the address
values in the P2 and MXAX and the address value indirectly specified by the Ri register allows the
processor to access the full 24-bit data address range when executing a MOVX @Ri, A or MOVX A, @Ri
instruction. The DPTR-related MOVX instructions do not utilize the P2 and MXAX register. Note that the
MXAX register is only used for 24-bit addressing when the processor is operating in either the 24-bit
paged or 24-bit contiguous modes. It can be utilized as a scratchpad SRAM register in 16-bit address
mode.
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