Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 100)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
100
External Memory Access
The DS80C400 follows the memory interface convention established by the industry standard 80C32/80C52 but with many added
improvements. Most notably, the device incorporates a 24-bit addressing capability that directly supports up to 16MB of program mem-
ory and 4MB of data memory. Externally, the memory is accessed through a multiplexed or demultiplexed 22-bit address bus/8-bit data
bus and eight chip-enable signals (active during program memory access) or four peripheral-enable signals (active during data mem-
ory access). Multiplexed addressing mode mimics the traditional 8051 memory interface with the address MSB presented on port 2
and the address LSB and data multiplexed on port 0. The multiplexed mode requires an external latch to demultiplex the address LSB
and data. When the MUX pin is pulled high, the address LSB and data are demultiplexed with the address MSB presented on port 2,
the address LSB on port 7, and the data on port 0. The elimination of the demultiplexing latch removes a delay element in the memo-
ry timing and can, in some cases, allow the use of slower, less expensive memory devices. Table 6-2 illustrates the locations of the
external memory control signals.
Table 6-2. External Memory Addressing Pin Assignments
Each upper-order address line (A16–A21) and chip or peripheral enable is individually enabled by the P4CNT, P5CNT, and P6CNT reg-
isters. Enabling upper-order address lines increases the maximum size of the external memories that can be addressed, and enabling
chips or peripheral enables control the number of external memories that can be addressed. For example, if P4CNT.5-3 are set to 010b,
A17 and A16 are enabled (along with A15–A0), permitting each chip-enable access a maximum memory device size of 2 18 or 256kB.
Note that the desired chip-enable signals must be enabled in order to become active for a defined memory range.
The configurable program/code chip-enable (CEx) and MOVX chip-enable (PCEx) signals issued by the microcontroller are used when
accessing multiple external memory devices. External chip-enable lines are only required if more than one physical block of memory
are used. In the standard 8051 configuration, PSEN is used as the output enable for the program memory device, and RD and WR con-
trol the input or output functions of the data (SRAM) device. Typically, the chip enables of the program and data memory devices can
be connected to their active state if only one of each is used. To support a larger amount of memory, however, the microcontroller must
generate chip or data enables to select one of several memory devices. Tables 6-3 through 6-5 demonstrate how to enable various
combinations of high-order address lines and chip enables.
SIGNAL MULTIPLEXED (MUX = 0) DEMULTIPLEXED (MUX = 1)
A21 P6.5 P6.5
A20 P6.4 P6.4
A19 P4.7 P4.7
A18 P4.6 P4.6
A17 P4.5 P4.5
A16 P4.4 P4.4
A15–A8 P2.7–P2.0 P2.7–P2.0
ADDRESS
A7–A0 P0.7–P0.0 P7.7–P7.0
DATA D7–D0 P0.7–P0.0 P0.7–P0.0
CE7 P6.3 P6.3
CE6 P6.2 P6.2
CE5 P6.1 P6.1
CE4 P6.0 P6.0
CE3 P4.3 P4.3
CE2 P4.2 P4.2
CE1 P4.1 P4.1
CHIP ENABLES
CE0 P4.0 P4.0
PCE2 P5.7 P5.7
PCE1 P5.6 P5.6
PCE0 P5.5 P5.5
PERIPHERAL
CHIP ENABLES
— P5.4 P5.4
Maxim Integrated