Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 39)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
39
Extended Stack Pointer Register (ESP)
Address Page Register (AP)
7 6 5 4 3 2 1 0
SFR 9Bh — — — — — — ESP.1 ESP.0
RW-1 RW-1 RW-1 RW-1 RW-1 RW-1 RW-0 RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
7 6 5 4 3 2 1 0
SFR 9Ch AP.7 AP.6 AP.5 AP.4 AP.3 AP.2 AP.1 AP.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
AP.7–0
Bits 7–0 Address page register. The address page register (AP) is a paging register, which is used with the 24-
bit paged addressing mode to support extended 24-bit program and data addressing capabilities, and
is fully compatible with the original 8052 16-bit addressing operation. The AP register and the higher-
order byte of the program counter (PC23: 16) are cleared to 00 hex, following a system reset, to estab-
lish initial program execution in the first 64kB page (page 0). When the microcontroller is programmed to
operate in the 24-bit paged addressing mode (AM1, AM0 = 01b), data programmed into the AP register
is loaded into the program counter high-order byte when the processor executes an LJMP or LCALL
instruction. Execution of any of these two instructions loads the AP into the high-order byte of the program
counter (PC23: 16) to allow the program counter (PC) to drive address lines A23–A16 with the previous
AP value at the same time as the lower 16 bits (A0–A15) of the PC are updated.
In this manner, software compiled using the standard 16-bit addressing scheme uses the contents of
the AP to establish the page to which the program flow is to jump. The AP register can be loaded at any
time prior to the execution of the above two instructions to establish the address vector, which is used
when the LJMP or LCALL instruction is used to cross page boundaries. Note that the third byte of the
program counter (PC23: 16) does not increment when the lower 16 bits in the lower two bytes of the PC
roll over from FFFF hex to 0000 hex. PC23: 16 functions only as a holding register to issue high-order
address (A23–A16) when the 24-paged addressing mode is enabled. All interrupts are handled by
pushing the high byte of the program counter (PC23: 16) along with the standard push of the standard
16-bit program counter on to the stack before the hardware generated interrupt LCALL instruction is
executed. The AP register is not altered during the interrupt and must be taken into consideration when
doing another LJMP or LCALL instruction within the interrupt routine.
Typically, it is best to do a PUSH AP when entering the interrupt routine, and a POP AP when exiting, if either
LJMP or LCALL instructions are to be used inside the routine with a new page address assigned to the AP.
The additional loading of PC23: 16 on to the stack results in one additional machine cycle during an interrupt
and three bytes being stored on the stack. Following the execution of a RETI instruction, the processor auto-
matically reloads the entire 24 value of the PC with the original address from the stack. Again, the RETI or
RET requires one additional machine cycle when compared to the standard 16-bit address-only operation.
The address page register is not used with the PC when the AM0 and AM1 bits are programmed for
either the 16-bit addressing or 24-bit contiguous addressing mode, but it is accessible as a general-pur-
pose SFR register.
Bits 7–2
ESP.1-0
Bits 1-0
Reserved.
Extended stack pointer. These extended stack pointer bits are used with SP to form a 10-bit stack
pointer to support the use of the 1kB of the internal data memory as stack memory. When SA = 1, any
overflow of the SP from FFh to 00h increments the ESP by 1, and any under flow of the SP from 00h to
FFh decrements the ESP by 1. The ESP register is not used as part of the stack pointer when the default
stack memory location is selected (SA = 0), but is still read/write accessible. Relocating the internal
MOVX SRAM through the IDM1: 0 bits does not alter the ability of the ESP and SP registers to properly
access the internal memory. See MCON register for more detail.
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