Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 77)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
77
Multiplier Control Register 1 (MCNT1)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
7 6 5 4 3 2 1 0
SFR D2h MST MOF SCB CLM — — — —
RW-0 R-0 RW-0 RW-0 R-1 R-1 R-1 R-1
MST
Bit 7
MOF
Bit 6
SCB
Bit 5
CLM
Bit 4
Bits 3-0
Multiply/accumulate status flag. The MST bit indicates the current status of the multiplier. When MST
is set to a 1 by the multiplier/accumulator hardware, it indicates that the multiplier/accumulator has not
completed an assigned task. Immediately after the processor begins loading data into the MA or MB
register, MST is automatically set and remains set until the assigned task is completed. There are no
restrictions on how quickly data is entered into the MA or MB registers. The only requirement to do a cal-
culation is to perform the load of MA, MB, and/or MCNT1 within the specified sequential relationship
associated with the requested task. MST is automatically cleared by the multiplier/accumulator hard-
ware once an assigned task is completed and the results are ready for the processor to read. A cleared
value in MST (0) also indicates that the accelerator is in an initialized state and can be loaded with new
values. Any data previously stored in MA or MB as the result or remainder of a previous calculation is
lost once new data is loaded into MA or MB. Data in the message center register is continually updat-
ed by the accumulation function and is preserved from one calculation to another. The processor soft-
ware can also clear the MST bit from a previous high state when the processor needs to initialize the
multiplier prior to the completion of a current operation. This action initializes the state machine action
within the accelerator, which allows the processor to immediately begin loading new data into MA and/or
MB to perform a new calculation. An additional initialization can be achieved if the MA register or MB
register is loaded prior to the completion of a current calculation. All previous calculation results are lost
as the accelerator resets the registers to begin accepting new data. In either of these forced clearing
methods, stored data in the message center accumulator register can become invalid.
Multiply overflow flag. The MOF flag bit is cleared to 0, following either a system reset or the initializa-
tion of the accelerator. The MOF bit is automatically set when the accelerator detects a divide-by-0 or
when the result of the calculation is larger than FFFF hex.
Shift carry bit. The SCB is used as a carry bit for shift operation when SCE (MCNT0.5) bit is set to 1.
Note that the SCB is not cleared at the beginning of a new operation and must be cleared by a write to
this bit or a system reset.
Clearing the MA, MB, and MC (accumulator) register. Setting the CLM bit clears the MA, MB, and MC
registers, and CLM is automatically cleared to a zero state following the clear operation. Writing a 0 to
this bit results in no operation.
Reserved.
Multiplier A Register (MA)
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
7 6 5 4 3 2 1 0
SFR D3h MA.7 MA.6 MA.5 MA.4 MA.3 MA.2 MA.1 MA.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
MA.7–0
Bits 7–0 Multiplier A register. The multiplier A (MA) register is used to load the 32-bit or 16-bit numerator when
the math accelerator is configured in a 32-bit by 16-bit or 16-bit by 16-bit divide mode. The multiplier A
register is also used to load the second value associated with a 16-bit by 16-bit calculation when the
accelerator is used in the multiply mode. A read of the MA register, following a completed function, pro-
vides the 32-bit result of a 32-bit by 16-bit divide, the 16-bit result of a 16-bit by 16-bit divide, the result
of a 16-bit by 16-bit multiplication calculation, the result of a normalized 32-bit calculation, or the result
of a shifted 32-bit calculation.
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