Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 62)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
62
Port 6 Control Register (P6CNT)
7 6 5 4 3 2 1 0
SFR B2h — — P6CNT.5 P6CNT.4 P6CNT.3 P6CNT.2 P6CNT.1 P6CNT.0
RT-1 RT-1 RT-1 RT-1 RT-1 RT-1 RT-1 RT-1
R = Unrestricted read, T = Timed-access write only, -n = Value after reset
P6.7–0
Bit 7
Bit 6
P6CNT.5–P6CNT.3
Bits 5–3
Port 6 control register. P6CNT bits provide the configuration for the alternate addressing modes on port
6. These settings, in turn, establish the size of the external program memory that can be accessed.
Programming the bit combinations given in this section converts the designated port 6 pins to I/O,
address, or chip enables. Once any bit combination containing a 1 is programmed into
P6CNT.2–P6CNT.0, the corresponding port pins that are then assigned to peripheral chip enables are
locked out from being programmed as I/O in the port 6 SFR. In a similar fashion, any bit combination con-
taining a 1 programmed into P6CNT.5–P6CNT.3 locks out the corresponding port pins assigned to
addresses for respective peripheral chip enables. This allows the normal use of the port 6 SFR, without
the concern that a byte write to the SFR would alter either any of the external chip enables or addresses.
Reserved.
Reserved.
Port pin P4.7 – P4.4 configuration control bit for PCEx. Note that setting these bits to values other than
those listed in the following table causes them to be treated as value of 000b and specifies peripheral
memory chip size to 32kB. The peripheral chip enables are configured by P5CNT.2–0, and are alternate
function of P5.7–4.
PCEx Address Line Selection
When CE0–CE7 are converted from program to program/data memory, PCE0–PCE3 is disabled if the
corresponding data memory area is covered by CEx. The internally decoded range for each program
chip enable (CE0–CE7) is established by the number of external address lines (A21–A16) enabled by the
P4CNT.5-P4CNT.3 control bits. The following table outlines the assigned memory boundaries of each
peripheral chip enable (PCEx) as determined by the P6CNT.5-P6CNT.3 control bits. Note that when the
external address bus is limited to A0–A15, the chip enables are internally decoded on a 32kB x 8-block
boundary. The peripheral chip-enable boundaries of the DS80C410/411 are different because the internal
64kB occupy the lower data memory space of the DS80C410/410. The setting of the PRAME bit does not
change the boundaries defined in these tables.
P6CNT.5–3 P4.7 P4.6 P4.5 P4.4
MAX. MEMORY
SIZE PER PCEx
000 I/O I/O I/O I/O 32kB
001 I/O I/O I/O A16 128kB
010 I/O I/O A17 A16 256kB
011 I/O A18 A17 A16 512kB
100 A19 A18 A17 A16 1MB
Maxim Integrated