Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 152)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
152
The error counters are not incremented as a result of condition 3. The CAN processor starts an overload frame at the first bit of an
expected intermission only if initiated by condition 1. Conditions 2 and 3 result in the CAN processor transmitting an overload frame
starting one bit after detecting the dominant bit. The overload flag consists of 6 dominant bits that correspond to an error flag. Because
the overload frame is only transmitted at the first bit time of the interframe space, it is possible for the CAN processor to discriminate
between an error frame and an overload frame. The overload flag destroys the intermission field. When such a condition is detected,
the CAN processor detects the overload condition and begins transmitting an overload frame. After the transmission of an overload
frame, the CAN processors monitor the bus for a dominant to recessive level change. The CAN processor then begins the transmis-
sion of 6 additional recessive bits for a total of 7 recessive bits on the bus. The overload delimiter consists of 8 recessive bits.
Initializing the CAN Controller
Software initialization of the CAN controller begins with the setting of the software initialization bit (SWINT) in the CAN 0 control SFR reg-
ister. When SWINT = 1, the CAN module is disabled and the CAN transmit output (C0TX) is placed in a recessive state. This, in turn,
allows the microcontroller to write information into the CAN MOVX SRAM control/status/mask registers without the possibility of cor-
rupting data transmissions or receptions in progress. Setting SWINT does not clear the receive- and transmit-error counters, but does
allow the microcontroller to write a common value to both error counters through the CAN 0 transmit-error SFR register. Consult the
description of the SWINT bit for specifics of the software initialization process.
All CAN registers located in the SFR memory map, with the exception of the CAN 0 control register, are cleared to a 00 hex following a
system reset. The CAN 0 control register is set to 07 hex following a system reset. CAN registers located in the MOVX memory map are
indeterminate following a system reset. A system reset also clears both the receive-error and transmit-error counters in the CAN con-
troller, takes the CAN processor offline, and sets the SWINT bit in the CAN 0 control register.
Following a reset, the following CAN-related registers must be initialized for proper operation of the CAN module. These registers are
in addition to specific registers associated with mask, format, or specific message centers.
CAN Interrupts
The CAN processor is assigned an interrupt that is individually enabled by the C0IE bit in the EIE register and globally enabled/dis-
abled by the EA bit in the IE SFR register. A CAN 0 interrupt can be generated by either a receive/transmit acknowledgment from one
of the 15 message centers or by a change in the CAN 0 status register.
CAN 0 transmit/receive interrupt sources are derived from a successful transmit or receive of data within one of the 15 message cen-
ters, as signaled by the INTRQ bit in the associated CAN 0 message (1–15) control register. Each message center (1–15) provides a
separate receive interrupt enable (ERI) and transmit interrupt enable (ETI) bits in the respective CAN 0 message (1–15) control regis-
ter to allow setting of the INTRQ bit in response to successful transmission or reception. The CAN 0 interrupt register (C0IR; A5h) SFR
can then be used to determine which message center generated the interrupt request. Software must clear the respective INTRQ bit
in the associated CAN 0 message (1–15) control register in order to clear the interrupt source before leaving the interrupt routine.
The CAN 0 interrupt source can also be connected to a change in the CAN 0 status register. Each of the bits in the CAN 0 status reg-
ister represents a potential source for the interrupt. To simplify the application and testing of a device, these sources are broken into
two groups that, for interrupt purposes, are enabled separately by the ERIE and STIE bits of the CAN 0 control (C0C) register. This
allows the nonstandard errors typically associated with development to be grouped under the STIE enable. These include the suc-
cessful receive RXS, successful transmit TXS, wake status WKS, and general set of error conditions reported by ER2–ER0. Also note
that, since the RXS and TXS bit are cleared by software, if a second message is received or transmitted before the RXS or TXS bits are
cleared and, after a read of the CAN 0 status register, a second interrupt is generated. The remaining error sources comprise the BSS
and EC96/128 bits in the CAN 0 status register. These read-only bits are separately enabled by the ERIE bit in the CAN 0 control reg-
ister. A read of the CAN 0 status register is required to clear either of the two groups of error interrupts. It is possible that multiple
changes to the status register can occur before the register is read; in that case, the status register generates only one interrupt. Figure
19-10 provides a graphical illustration of the interrupt sources and their respective interrupt enables.
REGISTER SIGNIFICANCE
P5CNT (SFR A2h) C0_I/O (P5CNT.3) must be set to enable CAN 0 pins P5.1 and P5.0.
C0BT0, C0BT1
(MOVX SRAM xxxx04-5)
These MOVX SRAM control registers must be set to configure CAN 0 (C0BT0, C0BT1) bus timing. The
exact values are dependent on the network configuration and environment.
COR (SFR CEh) C0BPR7-6 (COR.4-3) must be configured as part of the CAN 0 bus timing.
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