Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 82)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
82
Watchdog Control (WDCON)
R = Unrestricted read, W = Unrestricted write, T = Timed-access write only, -n = Value after reset, * = See description
7 6 5 4 3 2 1 0
SFR D8h SMOD_1 POR EPFI PFI WDIF WTRF EWT RWT
RW-0 RT-* RW-0 RW-* RT-0 RW-* RT-* RT-0
SMOD_1
Bit 7
POR
Bit 6
EPFI
Bit 5
PFI
Bit 4
WDIF
Bit 3
Serial modification. Setting this bit to 1 causes the baud rate for serial port 1 to be doubled in modes
1, 2, and 3. Clearing this bit disables the doubler.
Power-on reset flag. This bit indicates whether the last reset was a power-on reset. This bit is typically
interrogated following a reset. It must be cleared before the next reset of any kind for software to work
correctly. This bit is set following a power-on reset and is unaffected by all other resets.
Enable power-fail interrupt. Setting this bit to 1 enables the internal bandgap reference to generate a
power-fail interrupt when V
CC
falls below minimum V
CC
in normal operation. In stop mode, BGS (EXIF.0)
bit has to be set to enable a power-fail interrupt. Clearing this bit to 0 disables the power-fail interrupt.
Power-fail interrupt flag. This bit is set to a logic 1 when Vcc3 power-fail (V3PF) or Vcc1 power-fail
(V1PF) flags are set. Setting of PFI generates a power-fail interrupt request if enabled (EPFI = 1). The
V3PF (STATUS1.2) is set when V
CC
3 falls below Vpfw3, and the V1PF (STATUS1.3) is set when Vcc1 falls
below Vpfw1. The PFI bit must be cleared in software before exiting the interrupt service routine, or
another interrupt is generated. Clearing the PFI bit also clears the V3PF and V1PF flags. Setting this bit
by software generates a power-fail interrupt, if enabled. This bit is cleared by software or a power-fail
reset if Vcc3 is greater than Vpfw3 and Vcc1 is greater than Vpfw1 following the crystal startup time.
Watchdog interrupt flag. This bit is set to 1 by a watchdog timeout, which indicates a watchdog timer
event has occurred. When set, EWT (WDCON.1) and EWDI (EIE.4) determine the action to be taken.
This bit can only be modified using a timed-access procedure. Setting this bit in software generates a
watchdog interrupt, if enabled. This bit must be cleared in software before exiting the interrupt service
routine, or another interrupt, is generated.
EWT EWDI ACTIONS
0 0 No interrupt has occurred.
0 1 Watchdog interrupt has occurred.
1 0
No interrupt has been generated. Watchdog
reset occurs in 512 cycles if RWT is not set.
1 1
Watchdog interrupt has occurred. Watchdog
reset occurs in 512 cycles if RWT is not set.
WTRF
Bit 2
EWT
Bit 1
RWT
Bit 0
Watchdog timer reset flag. When set, this bit indicates that a watchdog timer reset has occurred. It is
typically interrogated to determine if a reset was caused by the watchdog timer. It is cleared by power-
on reset, but otherwise, it must be cleared by software before the next reset of any kind to allow soft-
ware to work correctly. Setting this bit by software does not generate a watchdog timer reset. If the EWT
bit is cleared, the watchdog timer has no effect on this bit.
Enable watchdog timer reset. Setting this bit to 1 enables the watchdog timer to reset the device;
clearing this bit to 0 disables the watchdog timer reset. It has no effect on the timer itself and its ability
to generate a watchdog interrupt. This bit can only be modified using timed-access procedure. The EWT
bit is cleared to a logic 0 on power-on reset and is unchanged by all other resets.
Reset watchdog timer. Setting this bit resets the watchdog timer count. This bit must be set using a
timed-access procedure before the watchdog timer expires, or a watchdog timer reset and/or interrupt
is generated if enabled. The timeout period is defined by CKCON.7-6 watchdog timer mode select bits.
When read, this bit is always 0.
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