Address filtering control – Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement User Manual
Page 181
High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
181
Figure 22-9. External Loopback Mode (MAC Control OM1:0 = 10b)
ADDRESS FILTERING CONTROL
The destination address of each Ethernet packet received by the MAC is examined by the address check block of the Ethernet con-
troller. The address check block and associated MAC control register bits that define the destination address-filtering mode are cov-
ered in the DS80C400 data sheet. The destination address is tested against the currently defined address filter, and the pass/fail sta-
tus is reported (by the BCU) to the filter fail (FF) bit of the receive status word. Additional status bits indicating whether the destination
address is a multicast or broadcast frame are also written by the BCU to the receive status word. Each receive packet, whether it pass-
es or fails the destination address filter, normally is written to the receive data buffer. In the same respect, as the PF bit is normally used
to indicate whether a frame was error-free, the FF bit normally is used to assess whether it passed the address filter, allowing the CPU
to quickly determine whether the packet should be processed or discarded. Table 22-3 summarizes the possible receive frames and
resulting PF, FF bit states reported in the receive status word.
Table 22-3. Packet Filter and Filter Fail Bit Status for Various Received Frames
RECEIVED FRAME
PF, FF
STATUS
BITS
NO ERRORS
WITH
ERRORS
PASSED
ADDRESS
FILTER
FAILED
ADDRESS FILTER
SPECIAL FILTERING CONDITION
ENABLED?
00
X
X
00
X
don’t care
don’t care
Promiscuous mode (PM = 1)
00
don’t care
don’t care
X
Broadcast frame AND DBF = 1
01
X
X
10
X
X
10
X
don’t care
don’t care
Promiscuous mode (PM = 1)
10
X
X
Pass bad frames (PB = 1)
11
X
X
11
X
X
Pass bad frames (PB = 1)
MDC
MII
MANAGEMENT
BLOCK
(Serial interface bus
to PHY)
MDIO
MII I/O BLOCK
(Transmit, receive,
and flow control)
EXTERNAL
PHY
DEVICE
(Configured to
loopback mode)
TX_EN
TXD[3:0]
RXCLK
RX_DV
RX_ER
RXD[3:0]
CRS
COL
TXCLK
DS80C400
Maxim Integrated