Port 4 control register (p4cnt) – Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement User Manual
Page 34
High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
34
Port 4 Control Register (P4CNT)
7
6
5
4
3
2
1
0
SFR 92h
-
-
P4CNT.5
P4CNT.4
P4CNT.3
P4CNT.2
P4CNT.1
P4CNT.0
RT-1
RT-1
RT-1
RT-1
RT-1
RT-1
RT-1
RT-1
R = Unrestricted read, T = Timed-access write only, -n = Value after reset
P4CNT.5–0
Bit 7
Bit 6
P4CNT.5-P4CNT.3
Port 4 control register. P4CNT bits provide the configuration for the alternate addressing modes on port
4 and 6. These settings, in turn, establish the size of the external program memory that can be accessed.
To prevent an unauthorized change in the external memory configuration, all writes to the P4CNT must
use the timed-access function. Programming the bit combinations given in this section converts the des-
ignated port pins to I/O, address, or chip enables. Once any bit combination containing a 1 is pro-
grammed into P4CNT.2-P4CNT.0, the corresponding port pins that are then assigned to chip enables are
locked out from being programmed as I/O in the port 4 SFR. In a similar fashion, any bit combination
containing a 1 programmed into P4CNT.5-P4CNT.3 locks out the corresponding port pins (P6.5-P6.4,
P4.7–P4.4) assigned to addresses. This allows the normal use of the port SFR, without the concern that
a byte write to the SFR alters any of the external chip enables or addresses. Following a reset, the P4CNT
is set to FFh, which, in turn, assigns all of the port 4 and P6.5-4 pins to address bits and chip enables.
This register should be programmed to reflect the actual system memory configuration.
Reserved.
Reserved.
Port pin P6.5, P6.4, P4.7–4 configuration control bits for CEx. Bits 5-0 configure the external mem-
ory control signals. P4CNT.5-3 determine whether specific P6 and P4 pins function as A21–A16 or I/O.
The number of external address lines enabled establishes the range for each program chip enable
(CE0-3) and data chip enable (PCE0-3). When P4CNT.5-3 = 000b, CE0–CE3 are decoded on 32kB
block boundaries.
CE0–CE7 can be individually configured as program or program/data memory by the MCON and
MCON1 SFRs. When CE0–CE7 are converted from program to program/data memory, PCE0–PCE3 are
disabled if the corresponding data memory area is covered by CEx. The internally decoded range for
each program chip enable (CE0–CE7) is established by the number of external address lines (A21–A16)
enabled by the P4CNT.5–P4CNT.3 control bits. The following table outlines the assigned memory bound-
aries of each chip enable (CEx) as determined by the P4CNT.5-P4CNT.3 control bits. (The memory
boundaries of each peripheral chip enable (PCEx) are determined by P6CNT.5-P6CNT.3.) Note that,
when the external address bus is limited to A0–A15, the chip enables are internally decoded on a 32kB
x 8 block boundary. This is to allow the use of the more common 32kB memories, as opposed to using
a less common 64kB block size memory.
PORT PIN FUNCTION
P4CNT.5-3
P6.5 P6.4 P4.7 P4.6 P4.5 P4.4
MAX
MEMORY
SIZE PER
CEx
000
I/O
I/O
I/O
I/O
I/O
I/O
32kB
001
I/O
I/O
I/O
I/O
I/O
A16
128kB
010
I/O
I/O
I/O
I/O
A17
A16
256kB
011
I/O
I/O
I/O
A18
A17
A16
512kB
100
I/O
I/O
A19
A18
A17
A16
1MB
101
I/O
A20
A19
A18
A17
A16
2MB
110 or 111
A21
A20
A19
A18
A17
A16
4MB
Maxim Integrated