Maxim Integrated High-Speed Microcontroller Users Guide: Network Microcontroller Supplement - Manual (Page 80)

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
80
PDCE7
Bit 3
PDCE6
Bit 2
PDCE5
Bit 1
PDCE4
Bit 0
Program/data chip enable 7. PDCE7 provides the software selection for CE7 to be used with either pro-
gram or program and data memory when CE7 is enabled by the port 6 control register (P6CNT). PDCE7
becomes a “don’t care” when CE7 is not enabled. The port 4 control register SFR establishes the spe-
cific address range for CE7. Write access to the memory block, which is connected to CE7 as data
memory (PDCE7 = 1), comes from the P3.6 WR signal. A read of the memory block connected to CE7
as program and data memory (PDCE7 = 1) comes from the PSEN signal, as opposed to the normal P3.7
RD signal when doing data memory reads.
PDCE7 = 0 enables CE7 as a program memory chip enable.
PDCE7 = 1 enables CE7 as a merged program and data memory chip enable.
Program/data chip enable 6. PDCE6 provides the software selection for CE6 to be used with either pro-
gram or program and data memory when CE6 is enabled by the port 6 control register (P6CNT). PDCE2
becomes a “don’t care” when CE6 is not enabled. The port 4 control register SFR establishes the spe-
cific address range for CE6. Write access to the memory block, which is connected to CE6 as data
memory (PDCE6 = 1), comes from the P3.6 WR signal. A read of the memory block connected to CE6
as program and data memory (PDCE6 = 1) comes from the PSEN signal, as opposed to the normal P3.7
RD signal when doing data memory reads.
PDCE6 = 0 enables CE6 as a program memory chip enable.
PDCE6 = 1 enables CE6 as a merged program and data memory chip enable.
Program/data chip enable 5. PDCE5 provides the software selection for CE5 to be used with either pro-
gram or program and data memory when CE5 is enabled by the port 6 control register (P6CNT). PDCE1
becomes a “don’t care” when CE5 is not enabled. The port 4 control register SFR establishes the spe-
cific address range for CE5. Write access to the memory block, which is connected to CE5 as data
memory (PDCE5 = 1), comes from the P3.6 WR signal. A read of the memory block connected to CE5
as program and data memory (PDCE5 = 1) comes from the PSEN signal, as opposed to the normal P3.7
RD signal when doing data memory reads.
PDCE5 = 0 enables CE5 as a program memory chip enable.
PDCE5 = 1 enables CE5 as a merged program and data memory chip enable.
Program/data chip enable 4. PDCE4 provides the software selection for CE4 to be used with either pro-
gram or program and data memory when CE04 is enabled by the port 6 control register (P6CNT).
PDCE4 becomes a “don’t care” when CE4 is not enabled. The port 4 control register SFR establishes
the specific address range for CE4. Write access to the memory block, which is connected to CE4 as
data memory (PDCE4 = 1), comes from the P3.6 WR signal. A read of the memory block connected to
CE4 as program and data memory (PDCE4 = 1) comes from the PSEN signal, as opposed to the nor-
mal P3.7 RD signal when doing data memory reads.
PDCE4 = 0 enables CE4 as a program memory chip enable.
PDCE4 = 1 enables CE4 as a merged program and data memory chip enable.
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